公开(公告)号：US5845100A

公开(公告)日：1998-12-01

申请号：US806022

申请日：1997-02-24

申请人： Ashwani Kumar Gupta ,  Glenn J. Hinton ,  Chan W. Lee

发明人： Ashwani Kumar Gupta ,  Glenn J. Hinton ,  Chan W. Lee

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30152 ,  G06F9/3816

摘要： A circuit and method for supplying a block of instruction code to an instruction buffer for an instruction decoder. A block of instruction code is fetched and input through a buffer input. A first instruction buffer and a second instruction buffer are coupled to the buffer input to store the block of instruction code. The output of the instruction buffers and a bypass bus coupled to the buffer input are input into an instruction buffer multiplexer. The instruction buffer multiplexer selects among the three inputs and outputs two blocks of instruction code to a rotator. The rotator receives an input pointer indicative of an initial byte. The rotator outputs a block of instruction code beginning at the initial byte to an instruction decoder.

摘要翻译： 一种用于向指令解码器的指令缓冲器提供指令代码块的电路和方法。 指令代码块通过缓冲器输入获取和输入。 第一指令缓冲器和第二指令缓冲器耦合到缓冲器输入端以存储指令代码块。 指令缓冲器的输出和耦合到缓冲器输入的旁路总线被输入到指令缓冲多路​​复用器。 指令缓冲多路​​复用器在三个输入端之间进行选择，并向转子输出两个指令代码块。 旋转器接收指示初始字节的输入指针。 旋转器将从初始字节开始的指令代码块输出到指令解码器。

公开(公告)号：US5758116A

公开(公告)日：1998-05-26

申请号：US316208

申请日：1994-09-30

申请人： Chan W. Lee ,  Gary L. Brown ,  Adrian L. Carbine ,  Ashwani Kumar Gupta

发明人： Chan W. Lee ,  Gary L. Brown ,  Adrian L. Carbine ,  Ashwani Kumar Gupta

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/04

CPC分类号： G06F9/30152 ,  G06F9/3816 ,  G06F9/382

摘要： A circuit and method for supplying output length marks indicative of the first bytes and last bytes of instructions in a block of instruction code to an instruction decoder. A block of instruction code is input to an input buffer. A plurality of programmable logic arrays (PLAs) is coupled to receive predetermined sets of bytes from the input buffer and to provide instruction information at an output. The output of the PLAs is coupled to fast carry chain circuitry, which serially processes the information from the PLAs and provides a START mark upon each finding of a first byte of an instruction and an END mark upon each finding of a last byte of an instruction. Length information is provided to wraparound logic for length calculations spanning into the next input buffer of instruction code. A FCC latch latches the output length marks from the fast carry chain circuitry and provides an output to the instruction decoder. If a length-varying prefix and a matching length-varying opcode are both present in an instruction, processing in the fast carry chain circuitry is aborted, and processing in slow carry chain circuitry is started. The slow carry chain circuitry processes information from a subset of the input buffer at a time, and thus requires more than one iteration, with a different set of PLA inputs provided by a multiplexer upon each iteration. A SCC latch latches the output length marks from the slow carry chain circuitry and provides an output to the instruction decoder.

摘要翻译： 一种用于将指示指令代码块中的指令的第一字节和最后字节的输出长度标记提供给指令解码器的电路和方法。 指令代码块被输入到输入缓冲器。 多个可编程逻辑阵列（PLAs）被耦合以从输入缓冲器接收预定的字节集合并在输出端提供指令信息。 PLA的输出耦合到快速进位链电路，其快速处理来自PLAs的信息，并且在每次发现指令的第一个字节时提供START标记，并且在每次发现指令的最后一个字节时提供END标记 。 长度信息被提供给跨越到指令代码的下一个输入缓冲器的长度计算的环绕逻辑。 FCC锁存器锁存来自快速进位链电路的输出长度标记，并向指令解码器提供输出。 如果长度变化的前缀和匹配的长度变化的操作码都存在于指令中，则快速进位链电路中的处理被中止，并且慢进位链电路中的处理开始。 慢进位链电路一次处理来自输入缓冲器的子集的信息，因此需要多于一次的迭代，在每次迭代时由多路复用器提供的不同的PLA输入集合。 SCC锁存器从慢进位链电路锁存输出长度标记，并向指令解码器提供输出。

公开(公告)号：US5608885A

公开(公告)日：1997-03-04

申请号：US205022

申请日：1994-03-01

申请人： Ashwani K. Gupta ,  Glenn J. Hinton ,  Chan W. Lee

发明人： Ashwani K. Gupta ,  Glenn J. Hinton ,  Chan W. Lee

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30152 ,  G06F9/3816

摘要： A circuit and method for supplying a block of instruction code to an instruction buffer for an instruction decoder. A block of instruction code is fetched and input through a buffer input. A first instruction buffer and a second instruction buffer are coupled to the buffer input to store the block of instruction code. The output of the instruction buffers and a bypass bus coupled to the buffer input are input into an instruction buffer multiplexer. The instruction buffer multiplexer selects among the three inputs and outputs two blocks of instruction code to a rotator. The rotator receives an input pointer indicative of an initial byte. The rotator outputs a block of instruction code beginning at the initial byte to an instruction decoder.

摘要翻译： 一种用于向指令解码器的指令缓冲器提供指令代码块的电路和方法。 指令代码块通过缓冲器输入获取和输入。 第一指令缓冲器和第二指令缓冲器耦合到缓冲器输入端以存储指令代码块。 指令缓冲器的输出和耦合到缓冲器输入的旁路总线被输入到指令缓冲多路​​复用器。 指令缓冲多路​​复用器在三个输入端之间进行选择，并向转子输出两个指令代码块。 旋转器接收指示初始字节的输入指针。 旋转器将从初始字节开始的指令代码块输出到指令解码器。

公开(公告)号：US6018786A

公开(公告)日：2000-01-25

申请号：US956375

申请日：1997-10-23

申请人： Robert F. Krick ,  Glenn J. Hinton ,  Michael D. Upton ,  David J. Sager ,  Chan W. Lee

发明人： Robert F. Krick ,  Glenn J. Hinton ,  Michael D. Upton ,  David J. Sager ,  Chan W. Lee

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F9/26 ,  G06F12/00

CPC分类号： G06F9/3808 ,  G06F12/0875 ,  G06F9/3802 ,  G06F9/3836

摘要： A cache memory is constituted with a data array and control logic. The data array includes a number of data lines, and the control logic operates to store a number of trace segments of instructions in the data lines, including trace segments that span multiple data lines. In one embodiment, each trace segment includes one or more trace segment members having one or more instructions, with each trace segment member occupying one data line, and the data lines of a multi-line trace segment being sequentially associated (logically). Retrieval of the trace segment members of a multi-line trace segment is accomplished by first locating the data line storing the first trace segment member of the trace segment, and then successively locating the remaining data lines storing the remaining trace segment members based on the data lines' logical sequential associations.

摘要翻译： 高速缓冲存储器由数据阵列和控制逻辑构成。 数据阵列包括许多数据线，并且控制逻辑操作以在数据线中存储多条迹线段，包括跨越多个数据线的迹线段。 在一个实施例中，每个跟踪段包括具有一个或多个指令的一个或多个跟踪段成员，每个跟踪段成员占据一个数据线，并且多行跟踪段的数据线被顺序地相关联（逻辑地）。 通过首先定位存储跟踪段的第一跟踪段成员的数据线，然后基于数据连续定位存储剩余跟踪段成员的剩余数据线，来检索多行跟踪段的跟踪段成员 行的逻辑顺序关联。

公开(公告)号：US06170038A

公开(公告)日：2001-01-02

申请号：US09447078

申请日：1999-11-22

申请人： Robert F. Krick ,  Glenn J. Hinton ,  Michael D. Upton ,  David J. Sager ,  Chan W. Lee

发明人： Robert F. Krick ,  Glenn J. Hinton ,  Michael D. Upton ,  David J. Sager ,  Chan W. Lee

IPC分类号： G06F926

CPC分类号： G06F12/0875

摘要： A cache memory is constituted with a data array and control logic. The data array includes a number of data lines, and the control logic operates to store a number of trace segments of instructions in the data lines, including trace segments that span multiple data lines. In one embodiment, each trace segment includes one or more trace segment members having one or more instructions, with each trace segment member occupying one data line, and the data lines of a multi-line trace segment being sequentially associated (logically). Retrieval of the trace segment members of a multi-line trace segment is accomplished by first locating the data line storing the first trace segment member of the trace segment, and then successively locating the remaining data lines storing the remaining trace segment members based on the data lines' logical sequential associations.

摘要翻译： 高速缓冲存储器由数据阵列和控制逻辑构成。 数据阵列包括许多数据线，并且控制逻辑操作以在数据线中存储多条迹线段，包括跨越多个数据线的迹线段。 在一个实施例中，每个跟踪段包括具有一个或多个指令的一个或多个跟踪段成员，每个跟踪段成员占据一个数据线，并且多行跟踪段的数据线被顺序地相关联（逻辑地）。 通过首先定位存储跟踪段的第一跟踪段成员的数据线，然后基于数据连续定位存储剩余跟踪段成员的剩余数据线，来检索多行跟踪段的跟踪段成员 行的逻辑顺序关联。

公开(公告)号：US07856633B1

公开(公告)日：2010-12-21

申请号：US09534191

申请日：2000-03-24

申请人： Chan W. Lee ,  Glenn Hinton ,  Robert Krick

发明人： Chan W. Lee ,  Glenn Hinton ,  Robert Krick

IPC分类号： G06F9/46 ,  G06F13/00

CPC分类号： G06F9/50 ,  G06F9/3017 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F12/0842 ,  G06F12/121

摘要： A method of partitioning a memory resource, associated with a multi-threaded processor, includes defining the memory resource to include first and second portions that are dedicated to the first and second threads respectively. A third portion of the memory resource is then designated as being shared between the first and second threads. Upon receipt of an information item, (e.g., a microinstruction associated with the first thread and to be stored in the memory resource), a history of Least Recently Used (LRU) portions is examined to identify a location in either the first or the third portion, but not the second portion, as being a least recently used portion. The second portion is excluded from this examination on account of being dedicated to the second thread. The information item is then stored within a location, within either the first or the third portion, identified as having been least recently used.

摘要翻译： 分割与多线程处理器相关联的存储器资源的方法包括定义存储器资源以分别包括专用于第一和第二线程的第一和第二部分。 然后，内存资源的第三部分被指定为在第一和第二线程之间共享。 在接收到信息项目（例如，与第一线程相关并且要存储在存储器资源中的微指令）时，检查最近最少使用（LRU）部分的历史以识别在第一或第三 部分，而不是第二部分，作为最近最少使用的部分。 第二部分由于专用于第二线程而被排除在本次考试之外。 然后将信息项目存储在第一或第三部分内，被标识为最近最少使用的位置内。