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公开(公告)号：US08286113B1
公开(公告)日：2012-10-09
申请号：US13004183
申请日：2011-01-11
IPC分类号： G06F17/50 , G06F15/177 , G06F9/00
CPC分类号： G06F17/5022 , G06F17/5054 , G06F2217/66
摘要： A system and method are provided for verifying implementation of a logic core in a complete bitstream. A logic core bitstream is extracted from the complete bitstream. The logic core bitstream is compared to a reference bitstream of the logic core for a target device. In response to no discrepancy in the comparison of the logic core bitstream and the reference bitstream, a data value is stored indicating that the logic core implementation contained in the complete bitstream is verified.
摘要翻译： 提供了一种用于验证完整比特流中的逻辑核的实现的系统和方法。 从完整比特流中提取逻辑核心比特流。 将逻辑核心比特流与用于目标设备的逻辑核心的参考比特流进行比较。 响应于逻辑核心比特流和参考比特流的比较中没有差异，存储指示包含在完整比特流中的逻辑核心实现被验证的数据值。
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2.发明授权Method and integrated circuit for protecting against differential power analysis attacks 有权用于防止差分功率分析攻击的方法和集成电路公开(公告)号：US08539254B1
公开(公告)日：2013-09-17
申请号：US12791608
申请日：2010-06-01
IPC分类号： H04L29/06
CPC分类号： H04L69/12 , H04L9/003 , H04L67/34 , H04L2209/12
摘要： In one embodiment of the invention, a method is provided for protecting against attacks on security of a programmable integrated circuit (IC). At least a portion of an encrypted bitstream input to the programmable IC is decrypted with a cryptographic key stored in the programmable IC. A number of failures to decrypt the encrypted bitstream is tracked. The tracked number is stored in a memory of the programmable IC that retains the number across on-off power cycles of the programmable IC. In response to the number of failures exceeding a threshold, data that prevents the decryption key from being used for a subsequent decryption of a bitstream is stored in the programmable IC.
摘要翻译： 在本发明的一个实施例中，提供了一种用于防止对可编程集成电路（IC）的安全性的攻击的方法。 输入到可编程IC的加密比特流的至少一部分被存储在可编程IC中的加密密钥解密。 跟踪解密加密比特流的许多失败。 被跟踪的号码存储在可编程IC的存储器中，该可编程IC保持可编程IC的开 - 关电源周期数。 响应于超过阈值的故障数量，防止解密密钥用于比特流的后续解密的数据被存储在可编程IC中。
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公开(公告)号：US08379850B1
公开(公告)日：2013-02-19
申请号：US12900805
申请日：2010-10-08
申请人： Brendan K. Bridgford , Stephen M. Trimberger , Jason J. Moore , Edward S. Peterson , James Wesselkamper , John C. Hoffman
发明人： Brendan K. Bridgford , Stephen M. Trimberger , Jason J. Moore , Edward S. Peterson , James Wesselkamper , John C. Hoffman
CPC分类号： H04L9/0822 , H04L9/003 , H04L9/0637
摘要： In one embodiment, a cryptographic device is provided. The cryptographic device includes a persistent memory and a decryption control circuit coupled to the persistent memory. The decryption control circuit is configured to receive an encrypted data stream and decrypt a first portion of the encrypted data stream using a first cryptographic key stored in the persistent memory, the first portion including a second cryptographic key. The decryption circuit is configured to decrypt a second portion of the encrypted data stream using the second cryptographic key, the second portion of the encrypted data stream including payload data.
摘要翻译： 在一个实施例中，提供了一种加密设备。 密码装置包括持久存储器和耦合到持久存储器的解密控制电路。 解密控制电路被配置为使用存储在永久存储器中的第一密码来接收加密数据流并解密加密数据流的第一部分，第一部分包括第二加密密钥。 解密电路被配置为使用第二加密密钥来解密加密数据流的第二部分，加密数据流的第二部分包括有效载荷数据。
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公开(公告)号：US08443230B1
公开(公告)日：2013-05-14
申请号：US12969355
申请日：2010-12-15
申请人： Philip B. James-Roxby , Ralph D. Wittig , Brendan K. Bridgford , Robert M. McGee , Richard DeFelice
发明人： Philip B. James-Roxby , Ralph D. Wittig , Brendan K. Bridgford , Robert M. McGee , Richard DeFelice
IPC分类号： G06F11/00
CPC分类号： G06F11/1641 , G06F11/1683
摘要： Methods and systems for redundant operation of a first and second processor are provided. A set of instructions is executed in parallel on the first and second processors. In response to a first access transaction for a peripheral device being issued from execution of an instruction by the first processor, the first processor suspends operation. In response to the first access transaction being a write transaction, the write transaction is not issued to the peripheral device until the second processor executes the instruction and issues a second access transaction that is equal to the write transaction. In response to the first access transaction being a read transaction, the read transaction is not issued to the peripheral device until the second processor executes the instruction.
摘要翻译： 提供了用于第一和第二处理器的冗余操作的方法和系统。 一组指令在第一和第二处理器上并行执行。 响应于由第一处理器执行指令而发出的用于外围设备的第一访问事务，第一处理器暂停操作。 响应于作为写事务的第一访问事务，在第二处理器执行指令并发出等于写事务的第二访问事务之前，不向外围设备发出写事务。 响应于作为读取事务的第一访问事务，在第二处理器执行指令之前，不向外围设备发出读取事务。
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公开(公告)号：US08166366B1
公开(公告)日：2012-04-24
申请号：US11975961
申请日：2007-10-22
CPC分类号： G06F11/10
摘要： Partial configuration of programmable circuitry with validation for an integrated circuit is described. An integrated circuit with programmable circuitry is obtained. The programmable circuitry is configured with a first bitstream in a non-dynamic mode of operation, after which the integrated circuit includes a configuration controller coupled to a buffer, an internal configuration access port, and an error checker. A portion of a second bitstream is loaded into the buffer for a dynamic partial configuration mode of operation. The portion of the second bitstream loaded into the buffer is validated with the error checker as being acceptable, after which the portion of the second bitstream is instantiated in the programmable circuitry via the internal configuration access port.
摘要翻译： 描述了具有集成电路验证的可编程电路的部分配置。 获得具有可编程电路的集成电路。 可编程电路配置有非动态操作模式的第一比特流，此后，集成电路包括耦合到缓冲器，内部配置访问端口和错误检查器的配置控制器。 第二比特流的一部分被加载到缓冲器中用于动态部分配置操作模式。 加载到缓冲器中的第二比特流的部分用错误检查器验证为可接受的，之后第二比特流的部分经由内部配置访问端口在可编程电路中被实例化。
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公开(公告)号：US07958394B1
公开(公告)日：2011-06-07
申请号：US11732782
申请日：2007-04-04
申请人： Brendan K. Bridgford
发明人： Brendan K. Bridgford
IPC分类号： G06F11/00
CPC分类号： G06F11/187 , G06F11/183 , G06F11/2215
摘要： A method of verifying a triple module redundant circuit. The method comprises providing three circuits, each comprising a redundant circuit; coupling a feedback voter circuit at the output of each circuit of the three circuits, each feedback voter receiving the output of each of the three circuits; disabling a first circuit of the three circuits; enabling the first circuit; disabling a second circuit of the three circuits; and verifying the output of the triple module redundant design to determine whether an error has occurred. A article of manufacture for verifying a design implemented as a triple redundancy module is also described.
摘要翻译： 一种验证三模块冗余电路的方法。 该方法包括提供三个电路，每个电路包括冗余电路; 在三个电路的每个电路的输出端耦合反馈选择电路，每个反馈选择器接收三个电路中的每一个的输出; 禁用三路电路的第一电路; 启用第一个电路; 禁用三路电路的第二电路; 并验证三重模块冗余设计的输出，以确定是否发生错误。 还描述了用于验证被实现为三重冗余模块的设计的制造品。
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公开(公告)号：US07506210B1
公开(公告)日：2009-03-17
申请号：US10606728
申请日：2003-06-26
申请人： Brendan K. Bridgford
发明人： Brendan K. Bridgford
IPC分类号： G06F11/00
CPC分类号： G01R31/31705 , G01R31/318533
摘要： Methods and tools for detecting and correcting problems arising in the configuration process of a programmable logic device are described. An analyzer is used to aid a user in debugging the configuration process. The analyzer can access the programmable logic device through a boundary scan architecture such as JTAG. The analyzer can step through the configuration process, capturing the data received by the programmable logic device at each step, and compare that captured data with expected data. Mismatches can indicate errors in the configuration process, and the analyzer can help a user correct such errors.
摘要翻译： 描述了用于检测和纠正在可编程逻辑器件的配置过程中出现的问题的方法和工具。 分析仪用于帮助用户调试配置过程。 分析仪可以通过边界扫描架构（如JTAG）访问可编程逻辑器件。 分析仪可以逐步完成配置过程，在每个步骤捕获可编程逻辑器件接收到的数据，并将捕获的数据与预期数据进行比较。 不匹配可能表示配置过程中的错误，分析仪可以帮助用户纠正这些错误。
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