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    Memory having and method for providing a reduced access time
    7.
    发明授权
    Memory having and method for providing a reduced access time 失效
    存储器和提供减少的存取时间的方法

    公开(公告)号：US5745429A

    公开(公告)日：1998-04-28

    申请号：US520241

    申请日：1995-08-28

    申请人： Timothy B. Cowles ,  Troy A. Manning ,  Todd A. Merritt

    发明人： Timothy B. Cowles ,  Troy A. Manning ,  Todd A. Merritt

    IPC分类号： G11C8/06 ,  G11C8/18 ,  G11C8/00

    CPC分类号： G11C8/18 ,  G11C8/06

    摘要： A memory device includes an array of memory cells that are arranged in row and columns. A row latch receives a row address and a latch signal and stores the row address in response to a transition of the latch signal. A row decoder is coupled between the latch and the array. In response to a transition of a row address strobe, which occurs a first predetermined time after the transition of the latch signal, the row decoder fires a row of the memory cells that are identified by the row address.

    摘要翻译： 存储器件包括排列成行和列的存储器单元阵列。 行锁存器接收行地址和锁存信号，并且响应于锁存信号的转变而存储行地址。 行解码器耦合在锁存器和阵列之间。 响应于在锁存信号转换之后的第一预定时间发生的行地址选通器的转变，行解码器触发由行地址识别的一行存储器单元。

    METHOD FOR ERROR TEST, RECORDATION AND REPAIR
    8.
    发明申请
    METHOD FOR ERROR TEST, RECORDATION AND REPAIR 失效
    错误测试，记录和修复方法

    公开(公告)号：US20110209011A1

    公开(公告)日：2011-08-25

    申请号：US13098569

    申请日：2011-05-02

    申请人： Christian N. Mohr ,  Timothy B. Cowles

    发明人： Christian N. Mohr ,  Timothy B. Cowles

    IPC分类号： G06F11/20

    CPC分类号： G11C17/18 ,  G11C11/401 ,  G11C29/24 ,  G11C29/44 ,  G11C29/70 ,  G11C29/838 ,  G11C2029/1208 ,  G11C2029/4402

    摘要： In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.

    摘要翻译： 在存储器装置中，提供了一种片上寄存器，其被配置为存储行地址以及测试失败的存储器单元的列地址。 存储行地址可以将测试限制为一次只激活与常见冗余段相关的行。 存储行地址还可以使用分段冗余来指导修复。 作为补充或替代，信息可以存储在反熔丝库中，该反熔丝库被设计成提供对冗余单元的访问，但是尚未启用对该单元的访问。 如果存储在反熔丝组中的信息与冗余单元的故障相关，则可以使用这样的信息来避免用该冗余单元进行修复。

    Method for error test, recordation and repair
    9.
    发明授权
    Method for error test, recordation and repair 有权
    错误测试，记录和修复方法

    公开(公告)号：US07941712B2

    公开(公告)日：2011-05-10

    申请号：US11714348

    申请日：2007-03-06

    申请人： Christian N. Mohr ,  Timothy B. Cowles

    发明人： Christian N. Mohr ,  Timothy B. Cowles

    IPC分类号： G11C29/00

    CPC分类号： G11C17/18 ,  G11C11/401 ,  G11C29/24 ,  G11C29/44 ,  G11C29/70 ,  G11C29/838 ,  G11C2029/1208 ,  G11C2029/4402

    摘要： In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test. Storing the row address frees testing from being limited to activating at one time only rows related to a common redundant segment. Storing the row address also guides repair using segmented redundancy. As an addition or alternative, information may be stored in an anti-fuse bank that is designed to provide access to a redundant cell but has not yet enabled access to that cell. If the information stored in the anti-fuse bank relates to the failure of the redundant cell, such information may be used to avoid repairing with that redundant cell.

    摘要翻译： 在存储器装置中，提供了一种片上寄存器，其被配置为存储行地址以及测试失败的存储器单元的列地址。 存储行地址可以将测试限制为一次只激活与常见冗余段相关的行。 存储行地址还可以使用分段冗余来指导修复。 作为补充或替代，信息可以存储在反熔丝库中，该反熔丝库被设计成提供对冗余单元的访问，但是尚未启用对该单元的访问。 如果存储在反熔丝组中的信息与冗余单元的故障相关，则可以使用这样的信息来避免用该冗余单元进行修复。

    ISOLATION CIRCUIT
    10.
    发明申请
    ISOLATION CIRCUIT 有权
    隔离电路

    公开(公告)号：US20090224242A1

    公开(公告)日：2009-09-10

    申请号：US12468482

    申请日：2009-05-19

    申请人： Timothy B. Cowles ,  Aron T. Lunde

    发明人： Timothy B. Cowles ,  Aron T. Lunde

    IPC分类号： H01L23/00 ,  H01L27/10 ,  H01L21/8232

    CPC分类号： G01R31/2884

    摘要： An isolation circuit, comprising a first transistor having a gate, a first source/drain terminal, and a second source/drain terminal, a first pad coupled to the gate of the first transistor, the first pad operable to receive an enable signal, a second pad coupled to the first source/drain of the first transistor, the second pad operable to receive a ground potential, a first fuse device coupling the second source/drain terminal to a node, a second fuse device coupling the node to the first pad, a third pad operable to receive a signal to be applied to at least one die, and a second transistor operable to selectively transfer the signal received at the third pad to the at least one die in response to a control signal provided by the node.

    摘要翻译： 一种隔离电路，包括具有栅极的第一晶体管，第一源极/漏极端子和第二源极/漏极端子，耦合到第一晶体管的栅极的第一焊盘，第一焊盘可操作以接收使能信号， 第二焊盘，其耦合到第一晶体管的第一源极/漏极，第二焊盘可操作以接收接地电位;将第二源极/漏极端子耦合到节点的第一熔丝器件;将节点耦合到第一焊盘的第二熔丝器件 第三焊盘，其可操作以接收要施加到至少一个管芯的信号;以及第二晶体管，其可操作以响应于由所述节点提供的控制信号选择性地将在第三焊盘处接收的信号传输到至少一个管芯。