Abstract:
A multi-lane analog-to-digital converter (ADC) is disclosed that is capable of compensating for one or more of its impairments such that its digital output accurately represents its analog input. The multi-lane ADC can compensate for unwanted phase offsets between multiple phases of a sampling clock used by the multi-lane ADC, unwanted bandwidth mismatches between lanes in the multi-lane ADC, and/or unwanted gain mismatches between the lanes in the multi-lane ADC to provide some examples.
Abstract:
An electrical circuit comprising a line driver for providing Ethernet signals is disclosed. The line driver comprises a voltage mode line driver for producing 1000BT and 100BT Ethernet signals and an active output impedance line driver arranged parallel to the voltage mode line driver. The line driver is capable of producing 1000BT or 100BT or 10BT Ethernet signals, wherein either the voltage mode line driver or the active impedance line driver is active.