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公开(公告)号：US20170244585A1
公开(公告)日：2017-08-24
申请号：US15061248
申请日：2016-03-04
Applicant: Broadcom Corporation
CPC classification number: H04L27/12 , H04B1/0007 , H04B1/0071 , H04B1/04 , H04L27/362
Abstract: A wireless transmitter processing chain includes digital radio frequency mixing circuitry to generate, in digital form, a representation of a transmit signal including multiple communication channels. From the digital representation, a wideband digital to analog converter creates the analog transmit signal that includes the communication channels. Individual mixers and filters follow, with mixing frequencies tuned to place the communication channels at the desired frequency centers.
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公开(公告)号：US09362940B2
公开(公告)日：2016-06-07
申请号：US14565017
申请日：2014-12-09
Applicant: Broadcom Corporation
Inventor： Jan Mulder
CPC classification number: G11C27/02 , G11C27/026 , H03M1/1245 , H03M1/168 , H03M1/442
Abstract: A parallel sample-and-hold circuit includes a sampling switch and a hold capacitor for each of the ADC and MDAC of a converter stage for a pipelined ADC. Each sampling switch couples the analog input of the first converter stage to its hold capacitor at the time a sample is desired to be taken. After the sample is placed on the hold capacitor, the sampling switch is opened and the hold capacitor stores the sample. To compensate for mismatches in the signal paths of these sample-and-hold circuits, a compensation switch is further used. The compensation switch couples the terminals of the hold capacitors together, creating a parallel sample-and-hold circuit. The compensation switch is controlled such that it is closed after the sampling switches are opened to equalize a voltage of the samples.
Abstract translation: 并行采样保持电路包括用于流水线ADC的转换器级的每个ADC和MDAC的采样开关和保持电容。 每个采样开关在需要采样时将第一转换器级的模拟输入耦合到其保持电容。 将样品放置在保持电容上后，采样开关打开，保持电容器存储样品。 为了补偿这些采样和保持电路的信号路径中的不匹配，进一步使用补偿开关。 补偿开关将保持电容器的端子耦合在一起，创建并行采样保持电路。 控制补偿开关使得在采样开关打开之后关闭，以均衡样品的电压。
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公开(公告)号：US20160149587A1
公开(公告)日：2016-05-26
申请号：US14565172
申请日：2014-12-09
Applicant: Broadcom Corporation
Inventor： Jan Mulder
IPC: H03M7/16
Abstract: A decoder for a current-steering digital-to-analog converter (DAC) is described herein. In an embodiment, the decoder is a dynamic element matching (DEM) row/column decoder that randomizes pairs of row control signals and column control signals that are provided to a matrix of current cells. The randomization is performed in a manner that ensures that the pairs of row control signals are randomized as pairs. In another embodiment, the decoder is an N-dimensional decoder, where N is any integer greater than two. The N-dimensional decoder comprises an N number of decoders that are each configured to provide respective control signals that are provided to current source(s) in current cell(s) in a respective dimension of an N-dimensional matrix of current cells for enabling current source(s) included therein. Such decoders advantageously allow for a simpler, more efficient design compared to a non-segmented, unary DAC due to the smaller area and lower power consumed.
Abstract translation: 本文描述了用于电流转向数模转换器（DAC）的解码器。 在一个实施例中，解码器是动态元素匹配（DEM）行/列解码器，其将提供给当前单元的矩阵的行控制信号和列控制信号的对随机化。 随机化以确保行对控制信号对成对地随机化的方式执行。 在另一个实施例中，解码器是N维解码器，其中N是大于2的任何整数。 N维解码器包括N个解码器，每个解码器被配置为提供在当前小区的N维矩阵的相应维度中提供给当前小区中的当前小区的各个控制信号，以使能 其中包括电流源。 与非分段一元DAC相比，这样的解码器有利地允许更简单，更有效的设计，因为较小的面积和更低的功耗。
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Patent Agency Ranking
公开(公告)号：US09543752B2
公开(公告)日：2017-01-10
申请号：US14042436
申请日：2013-09-30
Applicant: BROADCOM CORPORATION
Inventor： Jan Roelof Westra , Jan Mulder , Qiongna Zhang , Jeffrey Allan Riley , Davide Vecchi
CPC classification number: H02H3/20 , H01L23/60 , H01L27/0248 , H01Q1/50
Abstract: A device for digitally protecting against an overvoltage event may include a front-end circuit, an overvoltage protection circuit, and a protection switch. The protection switch may be coupled to the overvoltage protection circuit and may be configured to decouple the front-end circuit from an external medium, in response to a clamp signal. The overvoltage protection circuit may be configured to detect the overvoltage event at one or more nodes of a circuit. In response to the detection of the overvoltage event, the overvoltage protection circuit may generate the clamp signal to activate the protection switch.
Abstract translation: 用于数字防止过电压事件的装置可以包括前端电路，过电压保护电路和保护开关。 保护开关可以耦合到过电压保护电路，并且可以被配置为响应于钳位信号将前端电路与外部介质去耦。 过电压保护电路可以被配置为检测电路的一个或多个节点处的过电压事件。 响应于过电压事件的检测，过电压保护电路可产生钳位信号以激活保护开关。
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公开(公告)号：US09413385B2
公开(公告)日：2016-08-09
申请号：US14565172
申请日：2014-12-09
Applicant: Broadcom Corporation
Inventor： Jan Mulder
Abstract: A decoder for a current-steering digital-to-analog converter (DAC) is described herein. In an embodiment, the decoder is a dynamic element matching (DEM) row/column decoder that randomizes pairs of row control signals and column control signals that are provided to a matrix of current cells. The randomization is performed in a manner that ensures that the pairs of row control signals are randomized as pairs. In another embodiment, the decoder is an N-dimensional decoder, where N is any integer greater than two. The N-dimensional decoder comprises an N number of decoders that are each configured to provide respective control signals that are provided to current source(s) in current cell(s) in a respective dimension of an N-dimensional matrix of current cells for enabling current source(s) included therein. Such decoders advantageously allow for a simpler, more efficient design compared to a non-segmented, unary DAC due to the smaller area and lower power consumed.
Abstract translation: 本文描述了用于电流转向数模转换器（DAC）的解码器。 在一个实施例中，解码器是动态元素匹配（DEM）行/列解码器，其将提供给当前单元的矩阵的行控制信号和列控制信号的对随机化。 随机化以确保行对控制信号对成对地随机化的方式执行。 在另一个实施例中，解码器是N维解码器，其中N是大于2的任何整数。 N维解码器包括N个解码器，每个解码器被配置为提供在当前小区的N维矩阵的相应维度中提供给当前小区中的当前小区的各个控制信号，以使能 其中包括电流源。 与非分段一元DAC相比，这样的解码器有利地允许更简单，更有效的设计，因为较小的面积和更低的功耗。
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公开(公告)号：US20150149654A1
公开(公告)日：2015-05-28
申请号：US14132596
申请日：2013-12-18
Applicant: Broadcom Corporation
Inventor： Davide Vecchi , Jan Mulder , Franciscus Maria Leonardus Van der Goes , Erol Arslan , Michael Randall Grimwood
IPC: H04L29/06
CPC classification number: H04L65/608 , H04N21/42638 , H04N21/643
Abstract: A system may include a first stage comprising first signaling components for a first protocol, and a second stage comprising second signaling components for the first protocol and a second protocol. The system may further include logic configured to receive an incoming data stream, and determine a stream protocol for the data stream. The logic may be further configured to, responsive to the determination, activate the at least a portion of the first stage when the stream protocol is compliant with the first protocol, and when the stream protocol is compliant with the second protocol, deactivate the first stage.
Abstract translation: 系统可以包括第一级，其包括用于第一协议的第一信令组件，以及包括用于第一协议的第二信令组件和第二协议的第二级。 系统还可以包括被配置为接收输入数据流并且确定数据流的流协议的逻辑。 逻辑可以被进一步配置为：当流协议符合第一协议时，响应于确定激活第一级的至少一部分，并且当流协议符合第二协议时，停用第一级 。
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公开(公告)号：US20140084970A1
公开(公告)日：2014-03-27
申请号：US14094120
申请日：2013-12-02
Applicant: Broadcom Corporation
Inventor： Frank van der GOES , Christopher M. Ward , Jan Mulder , Ovidiu Bajdechi
IPC: H03K3/012
CPC classification number: H03K3/012 , H03F3/45192 , H03K19/0005 , H04L25/0278
Abstract: An electrical circuit comprising a line driver for providing Ethernet signals is disclosed. The line driver comprises a voltage mode line driver for producing 1000BT and 100BT Ethernet signals and an active output impedance line driver arranged parallel to the voltage mode line driver. The line driver is capable of producing 1000BT or 100BT or 10BT Ethernet signals, wherein either the voltage mode line driver or the active impedance line driver is active.
Abstract translation: 公开了一种包括用于提供以太网信号的线路驱动器的电路。 线路驱动器包括用于产生1000BT和100BT以太网信号的电压模式线路驱动器和与电压模式线路驱动器并联布置的有源输出阻抗线路驱动器。 线路驱动器能够产生1000BT或100BT或10BT以太网信号，其中电压模式线路驱动器或有源阻抗线路驱动器是活动的。
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公开(公告)号：US09325336B2
公开(公告)日：2016-04-26
申请号：US14497255
申请日：2014-09-25
Applicant: BROADCOM CORPORATION
Inventor： Jan Mulder
CPC classification number: H03M1/1009 , H03M1/1014 , H03M1/204 , H03M1/34 , H03M1/361
Abstract: A device for gain calibration of an analog-to-digital converter (ADC) residue amplifier includes a digital-to analog converter (DAC) configured to convert a digital signal to an analog signal. The DAC includes a calibration capacitor that can be used in the gain calibration of the ADC residue amplifier. A flash ADC, including a plurality of comparators and an additional comparator, generates the digital signal. The additional comparator provides a threshold voltage approximately in a middle point of a nominal subrange. The nominal subrange comprises a portion of a voltage range corresponding to threshold voltages of two adjacent comparators of the plurality of comparators.
Abstract translation: 用于模数转换器（ADC）残差放大器的增益校准的装置包括配置成将数字信号转换为模拟信号的数模转换器（DAC）。 DAC包括可用于ADC残差放大器增益校准的校准电容器。 包括多个比较器和附加比较器的闪存ADC产生数字信号。 额外的比较器提供大约在标称子范围的中点的阈值电压。 标称子范围包括与多个比较器的两个相邻比较器的阈值电压相对应的电压范围的一部分。
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