公开(公告)号：US20180122942A1

公开(公告)日：2018-05-03

申请号：US15383592

申请日：2016-12-19

Applicant: Broadcom Corporation

Inventor： Shom PONOTH ,  Akira Ito ,  Qing Liu

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7835 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1095

Abstract: Semiconductor devices are provided that use both silicon on insulator region and bulk region of a fully depleted silicon on insulator (FDSOI) device. For example, a semiconductor device includes a drain region that is disposed above a first type well and a first drain extension region that is disposed above the first type well and laterally spaced apart from the drain region. The semiconductor device further includes a second drain extension region that is disposed above the first type well and is laterally spaced apart from the drain region and the first drain extension region. The semiconductor device further includes a source region disposed above a second type well and laterally spaced apart from the second drain extension.

公开(公告)号：US20170018618A1

公开(公告)日：2017-01-19

申请号：US14929054

申请日：2015-10-30

Applicant: Broadcom Corporation

Inventor： Akira ITO ,  Shom PONOTH

IPC: H01L29/417 ,  H01L21/225 ,  H01L29/78 ,  H01L21/283 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/283 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78624 ,  H01L29/78654

Abstract: A field effect transistor (FET) with raised source/drain region of the device so as to constrain the epitaxial growth of the drain region. The arrangement of the spacer layer is created by depositing a photoresist over the extended drain layer during a photolithographic process.

Abstract translation: 一种场效应晶体管（FET），其具有该器件的升高源极/漏极区域，以限制漏极区域的外延生长。 间隔层的布置通过在光刻工艺中在延伸的漏极层上沉积光致抗蚀剂来产生。

公开(公告)号：US20150194433A1

公开(公告)日：2015-07-09

申请号：US14150245

申请日：2014-01-08

Applicant: BROADCOM CORPORATION

Inventor： Shom PONOTH ,  CHANGYOK PARK ,  JIAN-HUNG LEE ,  CHAO-YANG LU ,  GUANG-JYE SHIAU

IPC: H01L27/112 ,  H01L21/768 ,  H01L29/78 ,  G11C17/12

CPC classification number: H01L27/11206 ,  G11C17/12 ,  H01L27/0924 ,  H01L29/785

Abstract: A field-effect transistor (FET) based one-time programmable (OTP) device is discussed. The OTP device includes a fin structure, a gate structure, a first contact region, and a second contact region. The first contact region includes an insulating region and a conductive region and is configured to be electrically isolated from the gate structure. While, the second contact region includes the conductive region and is configured to be electrically coupled to at least a portion of the gate structure. The OTP device is configured to be programmed by disintegration of the insulating region in response to a first voltage being applied to the first contact and a second voltage being applied to the second contact region simultaneously, where the second voltage is higher than the first voltage by a threshold value.

Abstract translation: 讨论了基于场效应晶体管（FET）的一次可编程（OTP）器件。 OTP器件包括鳍结构，栅极结构，第一接触区域和第二接触区域。 第一接触区域包括绝缘区域和导电区域，并且被配置为与栅极结构电隔离。 而第二接触区域包括导电区域并且被配置为电耦合到栅极结构的至少一部分。 OTP装置被配置为通过响应于施加到第一触点的第一电压而破坏绝缘区域并且将第二电压同时施加到第二接触区域进行编程，其中第二电压高于第一电压，其中第二电压高于第一电压 一个阈值。