公开(公告)号：US09634014B2

公开(公告)日：2017-04-25

申请号：US14692552

申请日：2015-04-21

Applicant: Broadcom Corporation

Inventor： Qintao Zhang ,  Akira Ito

IPC: H01L27/112 ,  H01L21/28 ,  H01L23/525 ,  H01L21/265 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L29/423 ,  H01L21/3115

CPC classification number: H01L27/11206 ,  G11C17/146 ,  H01L21/26586 ,  H01L21/28158 ,  H01L21/31111 ,  H01L21/31155 ,  H01L23/5252 ,  H01L29/42368 ,  H01L29/66795 ,  H01L29/7851

Abstract: A programmable cell includes a split gate structure. The split gate structure includes a thin gate dielectric region and a thick gate dielectric region disposed below a gate conductor. A thickness of the thick oxide region is more than a thickness of the thin oxide region. The programmable cell can be fabricated using angle doping to dope an area associated with the thin dielectric region.

公开(公告)号：US20150357462A1

公开(公告)日：2015-12-10

申请号：US14309843

申请日：2014-06-19

Applicant: Broadcom Corporation

Inventor： Shom Surendran PONOTH ,  Akira Ito

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/0886 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7835 ,  H01L29/7851

Abstract: A lateral double-diffused MOS (LDMOS) bulk finFET device for high-voltage operation includes a first-well region and two or more second-well regions formed on a substrate material and one or more non-well regions including substrate material. The non-well regions are configured to separate well regions of the second-well regions. A source structure is disposed on a first fin that is partially formed on the first-well region. A drain structure is disposed on a second fin that is formed on a last one of the second-well regions. One or more dummy regions are formed on the one or more non-well regions. The dummy regions are configured to provide additional depletion region flow paths including vertical flow paths for charge carriers to enable the high-voltage operation.

Abstract translation: 用于高电压操作的横向双扩散MOS（LDMOS）体鳍鳍FETFET器件包括形成在衬底材料上的第一阱区域和两个或更多个第二阱区域以及包括衬底材料的一个或多个非阱区域。 非阱区域被配置为分离第二阱区域的阱区域。 源结构设置在部分地形成在第一阱区上的第一鳍上。 漏极结构设置在形成在第二阱区域的最后一个上的第二鳍片上。 在一个或多个非阱区域上形成一个或多个虚拟区域。 虚拟区域被配置为提供额外的耗尽区域流动路径，包括用于电荷载体的垂直流动路径以实现高电压操作。

公开(公告)号：US09105719B2

公开(公告)日：2015-08-11

申请号：US13737682

申请日：2013-01-09

Applicant: Broadcom Corporation

Inventor： Akira Ito

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7831 ,  H01L29/66484 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/785

Abstract: A semiconductor device includes a first well and a second well implanted in a semiconductor substrate. The semiconductor device further includes a gate structure above the first and second wells between a raised source structure and a raised drain structure. The raised source structure above is in contact with the first well and connected with the gate structure through a first semiconductor fin structure. The raised drain structure above and in contact with the second well and connected with a second semiconductor fin structure. The second semiconductor fin structure includes at least a gap and a lightly doped portion.

Abstract translation: 半导体器件包括注入半导体衬底中的第一阱和第二阱。 该半导体器件还包括位于升高的源极结构和升高的漏极结构之间的第一和第二阱之上的栅极结构。 上述升高的源极结构与第一阱接触并通过第一半导体鳍结构与栅极结构连接。 上升的漏极结构在第二阱上方并与第二阱接触并与第二半导体鳍结构连接。 第二半导体鳍结构至少包括间隙和轻掺杂部分。

公开(公告)号：US20150200196A1

公开(公告)日：2015-07-16

申请号：US14173744

申请日：2014-02-05

Applicant: BROADCOM CORPORATION

Inventor： Shom Surendran Ponoth ,  Akira Ito ,  Changyok Park

IPC: H01L27/112 ,  H01L29/66 ,  H01L23/525 ,  H01L29/78

CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L23/5252 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An anti-fuse device for fin field-effect transistor (finFET) technology includes a dummy gate, an electrically conductive contact, and a diffusion contact. The dummy gate is formed over an end-corner of a fin. The electrically conductive contact is disposed on a portion of the dummy gate and can be used as a first electrode of the device. The diffusion contact is disposed over the fin and can be used as a second electrode of the device.

Abstract translation: 用于鳍状场效应晶体管（finFET）技术的反熔丝器件包括虚拟栅极，导电触点和扩散接触。 虚拟门形成在翅片的端角上。 导电触点设置在虚拟栅极的一部分上，并且可以用作该器件的第一电极。 扩散接触件设置在翅片上并且可以用作该器件的第二电极。

公开(公告)号：US20130299904A1

公开(公告)日：2013-11-14

申请号：US13945739

申请日：2013-07-18

Applicant: Broadcom Corporation

Inventor： Akira Ito ,  Xiangdong Chen

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L29/7816 ,  H01L21/76224 ,  H01L23/5252 ,  H01L27/088 ,  H01L27/11206 ,  H01L27/11226 ,  H01L27/1124 ,  H01L27/11246 ,  H01L27/11266 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66681 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a pass gate dielectric, and a programming gate including a programming gate electrode and a programming gate dielectric. The programming gate is spaced from the pass gate by a drain extension region of the LDMOS structure. The LDMOS structure provides protection for the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate electrode. A method for producing such an OTP device comprises forming a drain extension region, fabricating a pass gate over a first portion of the drain extension region, and fabricating a programming gate over a second portion of the drain extension region.

Abstract translation: 根据一个实施例，具有横向扩散的金属氧化物半导体（LDMOS）结构的一次性可编程（OTP）器件包括包括通过栅极电极和通过栅极电介质的通过栅极，以及包括编程门 电极和编程栅极电介质。 编程门通过LDMOS结构的漏极扩展区与通过栅极间隔开。 当用于将编程栅极电介质破裂的编程电压施加到编程栅电极时，LDMOS结构为通路提供保护。 一种用于制造这种OTP器件的方法包括形成漏极延伸区域，在漏极延伸区域的第一部分上制造栅极通孔，以及在漏极延伸区域的第二部分上制造编程栅极。

公开(公告)号：US09478542B1

公开(公告)日：2016-10-25

申请号：US14817141

申请日：2015-08-03

Applicant: BROADCOM CORPORATION

Inventor： Akira Ito

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/70 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L21/265 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/26513 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/1079 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

Abstract: A semiconductor device includes a substrate having a well region implanted with a first dopant by a first well implantation and a non-doped section blocked from the first well implantation. The semiconductor device includes a semiconductor fin formed on the substrate, in which the semiconductor fin has a channel stop region and a channel region above the channel stop region. The channel stop region has a portion of the non-doped section and a portion of the well region. The semiconductor fin has a planar channel formed at an interface between the non-doped section and the channel region for additional current flow between source and drain regions of the semiconductor fin. The semiconductor device includes an isolation layer disposed adjacent to and in contact with the well region and the channel stop region. The semiconductor device also includes a gate structure disposed on the isolation layer and around the channel region.

Abstract translation: 半导体器件包括具有通过第一阱注入注入第一掺杂物的阱区和从第一阱注入阻挡的非掺杂区的衬底。 半导体器件包括形成在衬底上的半导体鳍片，其中半导体鳍片具有沟道停止区域和沟道区域上方的沟道区域。 沟道阻挡区域具有非掺杂区段的一部分和阱区域的一部分。 半导体鳍片具有形成在非掺杂部分和沟道区域之间的界面处的平面沟道，用于在半导体鳍片的源极和漏极区域之间的附加电流流动。 半导体器件包括邻近阱区和沟道阻挡区设置的隔离层。 半导体器件还包括设置在隔离层上并围绕沟道区的栅结构。

公开(公告)号：US20160190281A1

公开(公告)日：2016-06-30

申请号：US14611134

申请日：2015-01-30

Applicant: BROADCOM CORPORATION

Inventor： Qintao Zhang ,  Shom Surendran Ponoth ,  Akira Ito

IPC: H01L29/66 ,  H01L23/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/66553 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/28114 ,  H01L23/66 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An MOS device with increased drain-source voltage (Vds) includes a source region and a drain region deposited on a substrate. A gate region includes an inner spacer that extends the drain region. The inner spacer is formed attached to an isolation spacer that isolates the drain region from the gate region. The inner spacer is configured to extend the drain region to modify an electric field in a portion of a conductive band of the MOS device.

Abstract translation: 具有增加的漏极 - 源极电压（Vds）的MOS器件包括沉积在衬底上的源极区域和漏极区域。 栅极区域包括延伸漏极区域的内部间隔物。 内部间隔件形成附接到隔离间隔件，隔离间隔件将漏极区域与栅极区域隔离。 内部间隔件被配置为延伸漏极区域以修改MOS器件的导电带的一部分中的电场。

公开(公告)号：US09306057B2

公开(公告)日：2016-04-05

申请号：US13728264

申请日：2012-12-27

Applicant: Broadcom Corporation

Inventor： Akira Ito

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/08 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L29/7816 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7835

Abstract: A semiconductor device includes a first well and a second well implanted in a semiconductor substrate. The semiconductor device further includes a raised drain structure above and in contact with the second well and separate from the gate structure. The raised drain structure includes a drain connection point above the surface of the second well.

Abstract translation: 半导体器件包括注入半导体衬底中的第一阱和第二阱。 半导体器件还包括在第二阱上方并与第二阱接触并与栅极结构分离的升高的漏极结构。 升高的漏极结构包括在第二阱的表面上方的漏极连接点。

公开(公告)号：US20130302960A1

公开(公告)日：2013-11-14

申请号：US13945535

申请日：2013-07-18

Applicant: Broadcom Corporation

Inventor： Akira Ito ,  Xiangdong Chen

IPC: H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/76224 ,  H01L23/5252 ,  H01L27/088 ,  H01L27/11206 ,  H01L27/11226 ,  H01L27/1124 ,  H01L27/11246 ,  H01L27/11266 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66681 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a pass gate dielectric, and a programming gate including a programming gate electrode and a programming gate dielectric. The programming gate is spaced from the pass gate by a drain extension region of the LDMOS structure. The LDMOS structure provides protection for the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate electrode. A method for producing such an OTP device comprises forming a drain extension region, fabricating a pass gate over a first portion of the drain extension region, and fabricating a programming gate over a second portion of the drain extension region.

Abstract translation: 根据一个实施例，具有横向扩散的金属氧化物半导体（LDMOS）结构的一次性可编程（OTP）器件包括包括通过栅极电极和通过栅极电介质的通过栅极，以及包括编程门 电极和编程栅极电介质。 编程门通过LDMOS结构的漏极扩展区与通过栅极间隔开。 当用于将编程栅极电介质破裂的编程电压施加到编程栅电极时，LDMOS结构为通路提供保护。 一种用于制造这种OTP器件的方法包括形成漏极延伸区域，在漏极延伸区域的第一部分上制造栅极通孔，以及在漏极延伸区域的第二部分上制造编程栅极。

公开(公告)号：US20180122942A1

公开(公告)日：2018-05-03

申请号：US15383592

申请日：2016-12-19

Applicant: Broadcom Corporation

Inventor： Shom PONOTH ,  Akira Ito ,  Qing Liu

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7835 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1095

Abstract: Semiconductor devices are provided that use both silicon on insulator region and bulk region of a fully depleted silicon on insulator (FDSOI) device. For example, a semiconductor device includes a drain region that is disposed above a first type well and a first drain extension region that is disposed above the first type well and laterally spaced apart from the drain region. The semiconductor device further includes a second drain extension region that is disposed above the first type well and is laterally spaced apart from the drain region and the first drain extension region. The semiconductor device further includes a source region disposed above a second type well and laterally spaced apart from the second drain extension.