公开(公告)号：US20130175613A1

公开(公告)日：2013-07-11

申请号：US13782427

申请日：2013-03-01

Applicant: Broadcom Corporation

Inventor： Akira Ito ,  Xiangdon Chen

IPC: H01L21/28 ,  H01L29/78

CPC classification number: H01L21/28008 ,  H01L21/28035 ,  H01L29/105 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835

Abstract: According to one embodiment, a semiconductor device comprises a high-k gate dielectric overlying a well region having a first conductivity type formed in a semiconductor body, and a semiconductor gate formed on the high-k gate dielectric. The semiconductor gate is lightly doped so as to have a second conductivity type opposite the first conductivity type. The disclosed semiconductor device, which may be an NMOS or PMOS device, can further comprise an isolation region formed in the semiconductor body between the semiconductor gate and a drain of the second conductivity type, and a drain extension well of the second conductivity type surrounding the isolation region in the semiconductor body. In one embodiment, the disclosed semiconductor device is fabricated as part of an integrated circuit including one or more CMOS logic devices.

Abstract translation: 根据一个实施例，半导体器件包括覆盖在半导体本体中形成的具有第一导电类型的阱区的高k栅极电介质和形成在高k栅极电介质上的半导体栅极。 半导体栅极被轻掺杂，以具有与第一导电类型相反的第二导电类型。 所公开的可以是NMOS或PMOS器件的半导体器件还可以包括形成在半导体本体中的半导体栅极和第二导电类型的漏极之间的隔离区域，以及包围第二导电类型的漏极延伸阱 半导体体中的隔离区。 在一个实施例中，所公开的半导体器件被制造为包括一个或多个CMOS逻辑器件的集成电路的一部分。