公开(公告)号：US06298396B1

公开(公告)日：2001-10-02

申请号：US09088355

申请日：1998-06-01

申请人： Bruce A. Loyer ,  Thai H. Pham ,  David A. Spilo

发明人： Bruce A. Loyer ,  Thai H. Pham ,  David A. Spilo

IPC分类号： G06F1314

CPC分类号： G06F13/385

摘要： In a microcontroller employing a buffer descriptor ring direct memory access (DMA) unit, transmission of a packet can be split between multiple buffers. If an error occurs during the transmission of one of the buffers, the buffer descriptor ring DMA unit includes a provision that allows the software to reset the DMA channel to the first buffer containing the failed packet and to restart the transmission of the failed packet, rather than proceeding to the next packet.

摘要翻译： 在采用缓冲描述符环直接存储器访问（DMA）单元的微控制器中，分组的传输可以在多个缓冲器之间分离。 如果在一个缓冲器的传输期间发生错误，则缓冲器描述符环DMA单元包括允许软件将DMA通道复位到包含故障分组的第一缓冲器并重新启动故障分组的传输的规定，而不是 比继续下一个数据包。

公开(公告)号：US06212593B1

公开(公告)日：2001-04-03

申请号：US09088478

申请日：1998-06-01

申请人： Thai H. Pham ,  Patrick E. Maupin

发明人： Thai H. Pham ,  Patrick E. Maupin

IPC分类号： G06F1314

CPC分类号： G06F13/32

摘要： A microcontroller implements a buffer descriptor ring direct memory access (DMA) unit that can transmit a chained series of buffers without processor intervention. The buffers, however, include an interrupt on end-of-buffer flag that allows for an interrupt to be generated at the end of each buffer on a buffer-by-buffer basis.

摘要翻译： 微控制器实现缓冲描述符环直接存储器访问（DMA）单元，其可以在没有处理器干预的情况下传输链接的一系列缓冲器。 然而，缓冲区包括缓冲区结束标志上的中断，允许在逐个缓冲器的基础上在每个缓冲区的末尾生成一个中断。

公开(公告)号：US06493803B1

公开(公告)日：2002-12-10

申请号：US09378873

申请日：1999-08-23

申请人： Thai H. Pham ,  Pratik M. Mehta ,  Michael S. Quimby

发明人： Thai H. Pham ,  Pratik M. Mehta ,  Michael S. Quimby

IPC分类号： C06F1200

CPC分类号： G06F13/28

摘要： A direct memory access (DMA) controller provides seven DMA channels configurable for a PC/AT compatible mode or an enhanced mode. In an enhanced mode of the DMA controller, three DMA master channels on a master DMA controller and a DMA channel on a slave DMA controller are individually configurable to be either 8-bit or 16-bit DMA channels. In addition, in the enhanced mode, a memory address can increment or decrement across a memory page boundary. The DMA controller includes a transfer count register selectively configured for 16-bit operation or 24-bit operation. The DMA controller also includes address generation logic selectively configured for 24-bit operation or 28-bit operation. In the PC/AT compatible mode, the DMA controller supports three 16-bit channels and four 8-bit channels. The DMA controller thus provides DMA channel width configurability.

摘要翻译： 直接存储器访问（DMA）控制器提供可配置用于PC / AT兼容模式或增强模式的七个DMA通道。 在DMA控制器的增强模式下，主DMA控制器上的三个DMA主通道和从属DMA控制器上的DMA通道可以单独配置为8位或16位DMA通道。 此外，在增强模式中，存储器地址可以跨越存储器页边界递增或递减。 DMA控制器包括有选择地配置用于16位操作或24位操作的传输计数寄存器。 DMA控制器还包括有选择地配置用于24位操作或28位操作的地址生成逻辑。 在PC / AT兼容模式下，DMA控制器支持三个16位通道和四个8位通道。 因此，DMA控制器提供DMA通道宽度可配置性。

公开(公告)号：US5832278A

公开(公告)日：1998-11-03

申请号：US806440

申请日：1997-02-26

申请人： Thai H. Pham

发明人： Thai H. Pham

IPC分类号： G06F13/364

CPC分类号： G06F13/364

摘要： A two-level cascaded round robin arbiter. The arbiter arbitrates between a plurality of requesters for a shared resource in a round robin fashion. The arbiter comprises a series of first level arbiters which each receive a group of the plurality of requesters and select one requester in each group in a round robin manner. The first level arbiters operate in parallel to select their one requester thereby improving the overall selection time. The first level arbiters provide their selected requester to a second level arbiter which selects one group's selected requester to award use of the shared resource. The second level arbiter selects from among the groups in a round robin manner subject to an indication of a wrap condition provided by each of the first level arbiters to the second level arbiter. A wrap condition occurs when, in the process of selecting a requester, a first level arbiter has cycled from the previously selected requester through the fixed round robin order down to the lowest number requester and back up to the highest number requester. The second level arbiter continues to select the previously selected group as long as a wrap condition has not occurred in the previously selected group. Once a wrap condition has occurred, the second level arbiter selects the next group in the fixed cyclical order which has a currently active request. Each arbitration period the requester selected by the second level arbiter is latched and fed back to the first and second level arbiters which use the feedback history to select requesters according to the fixed cyclical round robin order.

摘要翻译： 一个两级级联循环仲裁器。 仲裁者以循环方式在多个请求者之间对共享资源进行仲裁。 仲裁器包括一系列第一级仲裁器，每个仲裁器接收一组多个请求者，并以循环方式选择每个组中的一个请求者。 第一级仲裁器并行操作以选择其一个请求者，从而改善整体选择时间。 第一级仲裁者将其选择的请求者提供给第二级仲裁器，其选择一组所选择的请求者来授予共享资源的使用。 第二级仲裁者以循环方式从组中选择，其中包括由每个第一级仲裁者向第二级仲裁器提供的包装条件的指示。 当在选择请求者的过程中，第一级仲裁者已经从先前选择的请求者通过固定轮询顺序循环到最低号码请求者并且返回到最高号码请求者时，发生包装条件。 只要先前选择的组中没有发生换行条件，第二级仲裁器继续选择先前选择的组。 一旦发生换行条件，第二级仲裁器选择具有当前活动请求的固定循环顺序的下一组。 由第二级仲裁者选择的请求者的每个仲裁期间被锁存并反馈给使用反馈历史的第一和第二等级仲裁器，以根据固定的周期性循环次序选择请求者。