公开(公告)号：US06493803B1

公开(公告)日：2002-12-10

申请号：US09378873

申请日：1999-08-23

申请人： Thai H. Pham ,  Pratik M. Mehta ,  Michael S. Quimby

发明人： Thai H. Pham ,  Pratik M. Mehta ,  Michael S. Quimby

IPC分类号： C06F1200

CPC分类号： G06F13/28

摘要： A direct memory access (DMA) controller provides seven DMA channels configurable for a PC/AT compatible mode or an enhanced mode. In an enhanced mode of the DMA controller, three DMA master channels on a master DMA controller and a DMA channel on a slave DMA controller are individually configurable to be either 8-bit or 16-bit DMA channels. In addition, in the enhanced mode, a memory address can increment or decrement across a memory page boundary. The DMA controller includes a transfer count register selectively configured for 16-bit operation or 24-bit operation. The DMA controller also includes address generation logic selectively configured for 24-bit operation or 28-bit operation. In the PC/AT compatible mode, the DMA controller supports three 16-bit channels and four 8-bit channels. The DMA controller thus provides DMA channel width configurability.

摘要翻译： 直接存储器访问（DMA）控制器提供可配置用于PC / AT兼容模式或增强模式的七个DMA通道。 在DMA控制器的增强模式下，主DMA控制器上的三个DMA主通道和从属DMA控制器上的DMA通道可以单独配置为8位或16位DMA通道。 此外，在增强模式中，存储器地址可以跨越存储器页边界递增或递减。 DMA控制器包括有选择地配置用于16位操作或24位操作的传输计数寄存器。 DMA控制器还包括有选择地配置用于24位操作或28位操作的地址生成逻辑。 在PC / AT兼容模式下，DMA控制器支持三个16位通道和四个8位通道。 因此，DMA控制器提供DMA通道宽度可配置性。

公开(公告)号：US06415348B1

公开(公告)日：2002-07-02

申请号：US09379457

申请日：1999-08-23

申请人： James O. Mergard ,  James R. Magro ,  Michael S. Quimby ,  Pratik M. Mehta

发明人： James O. Mergard ,  James R. Magro ,  Michael S. Quimby ,  Pratik M. Mehta

IPC分类号： G06F1338

CPC分类号： G06F13/4004

摘要： A microcontroller provides a flexible architecture to readily support both general embedded applications and communications applications. The microcontroller includes an embedded processor, a relatively low-speed general purpose peripheral bus controller, a relatively high-speed peripheral bus host bridge, a primary memory controller, and a secondary memory controller, each coupled to a processor bus. The general purpose peripheral bus controller is coupled to a relatively low-speed general purpose peripheral bus which is coupled to a plurality of integrated general purpose peripherals. The relatively high-speed peripheral bus host bridge is coupled to a relatively high-speed peripheral bus capable of supporting a plurality of communication-oriented peripherals. The secondary memory controller shares an address bus with the general purpose peripheral bus controller and shares a data bus with either the primary memory controller or the general purpose peripheral bus controller. The control timing of the secondary memory controller is independent of the control timing of the general purpose peripheral bus controller. Also, a processor arbiter is coupled to the embedded processor, and a relatively high-speed peripheral bus arbiter is coupled to the peripheral bus host bridge. Aside from the microcontroller, an embedded system can include a relatively low-speed general purpose peripheral bus and a relatively high-speed peripheral bus, both external to the microcontroller. The external relatively lowspeed general purpose bus can be coupled to the relatively low-speed general purpose peripheral bus controller, and the external relatively high-speed peripheral bus can be coupled to the relatively high-speed peripheral bus host bridge.

摘要翻译： 微控制器提供灵活的架构，以便于支持通用嵌入式应用和通信应用。 微控制器包括嵌入式处理器，相对低速的通用外围总线控制器，相对高速的外围总线主机桥，主存储器控制器和辅助存储器控制器，每个耦合到处理器总线。 通用外设总线控制器耦合到耦合到多个集成通用外设的相对低速的通用外设总线。 相对高速的外围总线主机桥耦合到能够支持多个面向通信的外围设备的相对高速的外围总线。 辅助存储器控制器与通用外设总线控制器共享地址总线，并与主存储器控制器或通用外设总线控制器共享数据总线。 辅助存储器控制器的控制时序与通用外设总线控制器的控制时序无关。 此外，处理器仲裁器耦合到嵌入式处理器，并且相对高速的外围总线仲裁器耦合到外围总线主机桥。 除了微控制器之外，嵌入式系统可以包括相对低速的通用外设总线和微控制器外部的相对高速的外围总线。 外部相对低速通用总线可以耦合到相对低速的通用外设总线控制器，外部相对高速的外设总线可以耦合到相对高速的外设总线主机桥。

公开(公告)号：US06401156B1

公开(公告)日：2002-06-04

申请号：US09379456

申请日：1999-08-23

申请人： James O. Mergard ,  James R. Magro ,  Michael S. Quimby ,  Pratik M. Mehta

发明人： James O. Mergard ,  James R. Magro ,  Michael S. Quimby ,  Pratik M. Mehta

IPC分类号： G06F1324

CPC分类号： G06F13/24

摘要： A microcontroller for PC/AT-compatible or non-PC/AT compatible embedded environments is disclosed. The microcontroller includes a general purpose bus which may emulate an ISA bus in a PC/AT-compatible mode. PC/AT-compatible DMA channels, interrupt controllers, programmable timers, a real-time clock, processor, and a flexible memory and an I/O mapping scheme are provided by the microcontroller. The programmable timers, interrupt controllers, DMA channels and I/O mapping can be configured for a PC/AT-compatible mode or a non-PC/AT-compatible mode. In particular, the plurality of interrupt controllers are configured such that some are enabled during PC/AT-compatible operation while the remainder are disabled. The microcontroller further embeds several PC/AT peripheral devices and yet maintains the flexibility to support external devices if desired by the embedded system designer. Other PC/AT-compatible features are also supported by the microcontroller.

摘要翻译： 公开了一种用于PC / AT兼容或非PC / AT兼容嵌入式环境的微控制器。 微控制器包括可以以PC / AT兼容模式来模拟ISA总线的通用总线。 微控制器提供PC / AT兼容的DMA通道，中断控制器，可编程定时器，实时时钟，处理器和灵活的存储器以及I / O映射方案。 可编程定时器，中断控制器，DMA通道和I / O映射可以配置为PC / AT兼容模式或非PC / AT兼容模式。 特别地，多个中断控制器被配置为使得一些在PC / AT兼容操作期间被启用，而剩余部分被禁用。 微控制器进一步嵌入了多个PC / AT外围设备，并且如果嵌入式系统设计者需要，则保持对外部设备的灵活性。 微控制器还支持其他PC / AT兼容功能。

公开(公告)号：US06499074B1

公开(公告)日：2002-12-24

申请号：US09379019

申请日：1999-08-23

申请人： Pratik M. Mehta ,  Michael S. Quimby

发明人： Pratik M. Mehta ,  Michael S. Quimby

IPC分类号： G06F1300

CPC分类号： G06F13/4226

摘要： A processor-oriented system, such as a microcontroller or computer system, supports a programmable address decoder used to redirect accesses to unassigned I/O address space. I/O accesses to unassigned addresses or address holes can be directed to multiple busses. If a programmable switch associated with the programmable address decoder is set to a first predetermined value, then certain I/O addresses are directed to a first bus. If the programmable switch associated with the programmable address decoder is set to a second predetermined value, then certain I/O addresses are directed to a second bus. If the first bus is coupled to PC/AT compatible peripheral devices and the second bus is coupled to non-PC/AT compatible devices, then the I/O address redirection capability selectively supports a PC/AT compatible mode or a non-PC/AT compatible mode. Certain integrated devices coupled to the second bus can be bypassed or disabled as desired to allow redirection of I/O to external devices coupled to the first bus.

摘要翻译： 诸如微控制器或计算机系统的面向处理器的系统支持用于重定向对未分配的I / O地址空间的访问的可编程地址解码器。 对未分配地址或地址孔的I / O访问可以被引导到多个总线。 如果与可编程地址解码器相关联的可编程开关被设置为第一预定值，则某些I / O地址被引导到第一总线。 如果与可编程地址解码器相关联的可编程开关被设置为第二预定值，则某些I / O地址被引导到第二总线。 如果第一总线耦合到PC / AT兼容的外围设备，并且第二总线耦合到非PC / AT兼容设备，则I / O地址重定向能力选择性地支持PC / AT兼容模式或非PC / AT兼容模式。 可以根据需要绕过或禁用耦合到第二总线的某些集成设备，以允许I / O重定向到耦合到第一总线的外部设备。

公开(公告)号：US20080280559A1

公开(公告)日：2008-11-13

申请号：US11744926

申请日：2007-05-07

申请人： Shree A. Dandekar ,  Pratik M. Mehta

发明人： Shree A. Dandekar ,  Pratik M. Mehta

IPC分类号： H04B7/00

CPC分类号： H04W12/04 ,  G06F9/4411 ,  H04W84/18 ,  H04W92/18

摘要： A method for sharing Bluetooth pairs across multiple operating system partitions. The method includes the steps of pairing a first operating system partition with a Bluetooth enabled device; determining when a memory of an information handling system includes an additional operating system partition; and, pairing the additional operating system partition with the Bluetooth enabled device when the additional operating system partition is present.

摘要翻译： 一种在多个操作系统分区上共享蓝牙对的方法。 该方法包括将第一操作系统分区与蓝牙设备配对的步骤; 确定信息处理系统的存储器何时包括附加的操作系统分区; 并且当附加操作系统分区存在时，将额外的操作系统分区与蓝牙设备配对。

公开(公告)号：US06681301B1

公开(公告)日：2004-01-20

申请号：US09969303

申请日：2001-10-02

申请人： Pratik M. Mehta ,  James R. Magro

发明人： Pratik M. Mehta ,  James R. Magro

IPC分类号： G06F1200

CPC分类号： G06F13/1694

摘要： A system that enables a memory controller to control data transfers with memory modules, such as DIMMs (double in-line memory modules), of either a “by 4” (×4) type or a non-by-4 type (non-×4). Both ×4 and non-×4 DIMMs may be used in the system simultaneously, and the memory controller dynamically adjusts its enable and other signals as needed. Data strobe signals are provided to and from DIMMs over a data strobe transfer circuits which in the case of a non-×4 DIMM handles data strobes for an entire byte of data, while in the case of ×4 DIMM the data transfer circuit handles data strobes for one nibble (four bits) of a byte of data. A hybrid data mask/data strobe transfer circuit handles the other nibble of a byte of data in the case of data transfers for ×4 DIMMs, and handles data mask signals for write operations for non-×4 DIMMs.

摘要翻译： 一种使内存控制器可以使用“by 4”（x4）类型或非4类（非x4）类型的内存模块（例如DIMM（双列直插式内存模块））控制数据传输的系统 ）。 x4和non-x4 DIMM都可以同时在系统中使用，并且存储器控制器根据需要动态调整其使能和其他信号。 数据选通信号通过数据选通传输电路提供给DIMM，数据选通传输电路在非x4 DIMM的情况下处理整个数据字节的数据选通，而在x4 DIMM的情况下，数据传输电路处理数据选通 一个字节数据的一个四位（四位）。 混合数据掩码/数据选通传输电路在x4 DIMM的数据传输的情况下处理一字节数据的另一半字节，并处理用于非x4 DIMM的写入操作的数据掩码信号。

公开(公告)号：US06490638B1

公开(公告)日：2002-12-03

申请号：US09379012

申请日：1999-08-23

申请人： Andrew Ha ,  Pratik M. Mehta

发明人： Andrew Ha ,  Pratik M. Mehta

IPC分类号： G06F1310

CPC分类号： G06F13/4217

摘要： A system provides a general purpose bus with programmable timing capability. As part of a microcontroller, this general purpose bus provides a mechanism for communication between general purpose peripherals connected to the bus and enables external devices to be connected with proper timing to the microcontroller. The general purpose bus controller includes programmable interface timing control logic which allows the bus cycle length for commands from a processor or other bus master to be programmed. Accordingly, memory and I/O read and write commands are customized to suit the timing requirements of peripheral devices connected externally to the microcontroller. A significant variety of peripheral devices may thus be coupled to the microcontroller without requiring additional glue logic. The general purpose bus controller further includes an echo mode which permits accesses to internal peripheral devices to be interpreted by a logic analyzer or other debugging equipment.

摘要翻译： 系统提供具有可编程定时能力的通用总线。 作为微控制器的一部分，这种通用总线提供了一种用于连接到总线的通用外设之间进行通信的机制，并使外部设备能够以适当的时序连接到微控制器。 通用总线控制器包括可编程接口定时控制逻辑，其允许来自处理器或其它总线主机的命令的总线周期长度被编程。 因此，存储器和I / O读写命令是定制的，以适应外部连接到微控制器的外设的时序要求。 因此，可以将显着的各种外围设备耦合到微控制器而不需要附加的胶合逻辑。 通用总线控制器还包括允许通过逻辑分析器或其他调试设备解释对内部外围设备的访问的回波模式。

公开(公告)号：US08261108B2

公开(公告)日：2012-09-04

申请号：US13048409

申请日：2011-03-15

申请人： Pratik M. Mehta ,  Luc Dinh Truong

发明人： Pratik M. Mehta ,  Luc Dinh Truong

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3287 ,  G06F1/3203 ,  Y02D10/171

摘要： An information handling system (IHS) is provided which includes a system processor and a wireless section coupled to the system processor. While the system processor remains in a reduced power state, the wireless section is operable to be powered up to detect the presence of a wireless network external to the IHS and determine if that detected wireless network matches a network included in profile information stored in a memory that is accessible by the wireless section. An indicator is coupled to the wireless section and is operable to provide an indication that a wireless network is present.

摘要翻译： 提供了一种信息处理系统（IHS），其包括耦合到系统处理器的系统处理器和无线部分。 当系统处理器保持在降低的功率状态时，无线部分可操作以上电以检测IHS外部的无线网络的存在，并且确定检测到的无线网络是否匹配包含在存储在存储器中的简档信息中的网络 可由无线部分访问。 指示符耦合到无线部分，并且可操作以提供无线网络存在的指示。

公开(公告)号：US20090089465A1

公开(公告)日：2009-04-02

申请号：US11862221

申请日：2007-09-27

申请人： David W. Douglas ,  Pratik M. Mehta ,  Bruce Montag

发明人： David W. Douglas ,  Pratik M. Mehta ,  Bruce Montag

IPC分类号： G06F13/38

CPC分类号： G06F3/1454 ,  G09G5/005 ,  G09G5/006 ,  G09G2370/047 ,  G09G2370/16

摘要： A method for conveying display device data over an ultra wideband wireless link that provides an information handling system with an information handling system ultra wideband communication link. The method also provides a display device with a display device ultra wideband communication link and transmits display data between the information handling system ultra wideband communication link and the display device ultra wideband communication link.

摘要翻译： 一种通过超宽带无线链路传送显示设备数据的方法，该超宽带无线链路向信息处理系统提供信息处理系统超宽带通信链路。 该方法还提供具有显示装置超宽带通信链路的显示装置，并且在信息处理系统超宽带通信链路和显示装置超宽带通信链路之间传送显示数据。

公开(公告)号：US20080090614A1

公开(公告)日：2008-04-17

申请号：US11548749

申请日：2006-10-12

申请人： Alan E. Sicher ,  Pratik M. Mehta

发明人： Alan E. Sicher ,  Pratik M. Mehta

IPC分类号： H04Q7/38

CPC分类号： H04W8/205

摘要： An improved method and system for removing operating restrictions associated with a predetermined subscriber identity module (SIM) from a wireless device. A user is allowed to securely log onto a Web site that contains support information on subscription plans, billing, termination, penalties, and device-to-SIM unlocking. After satisfying any outstanding contract terms and payment of termination or device unlock fees, the user initiates a device-to-SIM unlock procedure. A client application on the wireless device securely transfers subscription, system, and SIM information to a device-to-SIM unlock system which uses the information to generate appropriate unlock codes. The unlock codes are then securely transferred to the client application, which processes them to remove operating restrictions associated with the predetermined SIM from the device and allow it to thereafter implement a plurality of SIMs.

摘要翻译： 一种用于从无线设备去除与预定用户识别模块（SIM）相关联的操作限制的改进的方法和系统。 允许用户安全地登录到包含订阅计划，计费，终止，处罚和设备到SIM卡解锁支持信息的网站。 在满足任何未完成的合同条款和支付终止或设备解锁费用后，用户启动设备到SIM卡解锁程序。 无线设备上的客户端应用将订阅，系统和SIM卡信息安全地传送到使用该信息产生适当的解锁码的设备到SIM卡解锁系统。 然后将解锁码安全地传送到客户端应用程序，处理它们以从设备中移除与预定SIM卡相关联的操作限制，并允许其后执行多个SIM。