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公开(公告)号：US06260162B1
公开(公告)日：2001-07-10
申请号：US09183915
申请日：1998-10-31
IPC分类号： G06F1100
CPC分类号： G06F11/0757
摘要： A processor-oriented device provides a watchdog timer having a test mode programmable reset. When the device is placed in a test mode by pulling a test mode hardware pin during a reset of the timer and then an appropriate write key is provided to the timer, a watchdog timer reset count is writeable, allowing for a programmable duration for a watchdog timer reset. The watchdog timer reset count may be a reset duration value maintained by a watchdog timer reset counter. Based on both a test mode signal from watchdog timer test mode enable logic and a write key, watchdog timer reset write enable logic enables writes to the watchdog timer reset count.
摘要翻译： 面向处理器的设备提供具有测试模式可编程复位的看门狗定时器。 当在定时器复位期间通过拉动测试模式硬件引脚将器件置于测试模式，然后向定时器提供适当的写入键，看门狗定时器复位计数可写入，允许看门狗的可编程持续时间 定时器复位。 看门狗定时器复位计数可以是由看门狗定时器复位计数器维持的复位持续时间值。 基于看门狗定时器测试模式使能逻辑和写入键的测试模式信号，看门狗定时器复位写使能逻辑使能写入看门狗定时器复位计数。
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2.发明授权System for loading a current buffer desciptor register with a value different from current value to cause a previously read buffer descriptor to be read again 失效用于加载与当前值不同的值的当前缓冲区描述符寄存器的系统，以使再次读取先前读取的缓冲区描述符公开(公告)号：US06298396B1
公开(公告)日：2001-10-02
申请号：US09088355
申请日：1998-06-01
申请人： Bruce A. Loyer , Thai H. Pham , David A. Spilo
发明人： Bruce A. Loyer , Thai H. Pham , David A. Spilo
IPC分类号： G06F1314
CPC分类号： G06F13/385
摘要： In a microcontroller employing a buffer descriptor ring direct memory access (DMA) unit, transmission of a packet can be split between multiple buffers. If an error occurs during the transmission of one of the buffers, the buffer descriptor ring DMA unit includes a provision that allows the software to reset the DMA channel to the first buffer containing the failed packet and to restart the transmission of the failed packet, rather than proceeding to the next packet.
摘要翻译： 在采用缓冲描述符环直接存储器访问（DMA）单元的微控制器中，分组的传输可以在多个缓冲器之间分离。 如果在一个缓冲器的传输期间发生错误，则缓冲器描述符环DMA单元包括允许软件将DMA通道复位到包含故障分组的第一缓冲器并重新启动故障分组的传输的规定，而不是 比继续下一个数据包。
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3.发明授权Staggered polling of buffer descriptors in a buffer descriptor ring direct memory access system 失效在缓冲区描述符环直接存储器访问系统中对缓冲区描述符的交错轮询公开(公告)号：US06182165B2
公开(公告)日：2001-01-30
申请号：US09088200
申请日：1998-06-01
申请人： David A. Spilo
发明人： David A. Spilo
IPC分类号： G06F1314
CPC分类号： G06F13/28
摘要： A microcontroller implements a buffer descriptor ring direct memory access (DMA) unit that polls buffer descriptors when in idle mode. This polling is to determine whether the software has set up a buffer or group of buffers transmission and transfer ownership of those buffers to the DMA unit. To reduce interrupt latency and bandwidth occupation, the polling of these buffer descriptor ownership flags is staggered for the DMA channels. For example, if eight DMA channels are implemented, the polling of their buffer descriptors can be distributed throughout a 1.28 millisecond polling interval.
摘要翻译： 微控制器实现缓冲描述符环直接存储器访问（DMA）单元，其在空闲模式时轮询缓冲器描述符。 此轮询是确定软件是否已建立一个缓冲区或一组缓冲区传输，并将这些缓冲区的所有权转移给DMA单元。 为了减少中断延迟和带宽占用，这些缓冲区描述符所有权标志的轮询对于DMA通道是交错的。 例如，如果实现了八个DMA通道，则可以在整个1.28毫秒的轮询间隔内分配其缓冲区描述符的轮询。
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4.发明授权Technique for incorporating a built-in self-test (BIST) of a DRAM block with existing functional test vectors for a microprocessor 失效将DRAM块的内置自检（BIST）与现有的微处理器功能测试向量相结合的技术
公开(公告)号：US5748640A
公开(公告)日：1998-05-05
申请号：US711864
申请日：1996-09-12
申请人： Chongjun (June) Jiang , David A. Spilo , Timothy J. Baldwin , Robert D. Bryfogle , Bobby I. Pinkerton, Jr.
发明人： Chongjun (June) Jiang , David A. Spilo , Timothy J. Baldwin , Robert D. Bryfogle , Bobby I. Pinkerton, Jr.
IPC分类号： G06F11/267 , G11C29/10 , G11C29/44 , G11C29/50 , G06F11/00
CPC分类号： G06F11/2236 , G11C29/10 , G11C29/44 , G11C29/50
摘要： A processing unit having a CPU core, an integrated RAM and a test unit, which may be implemented in either a test unit, which may be implemented in either hardware or software. A built-in self-test of the RAM is designed to run concurrently with the functional vectors used to test the CPU core. Once the core tests have been activated, a control register may be written to by which will activate the built-in self-test. Thus, the BIST and core testing may overlap to minimize test time.
摘要翻译： 具有CPU核心，集成RAM和测试单元的处理单元，其可以在可以以硬件或软件实现的测试单元中实现。 RAM的内置自检被设计为与用于测试CPU内核的功能向量同时运行。 激活核心测试后，可能会写入一个控制寄存器，从而激活内置的自检。 因此，BIST和核心测试可能重叠以最小化测试时间。
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5.发明授权Data compression or decompressions during DMA transfer between a source and a destination by independently controlling the incrementing of a source and a destination address registers 失效通过独立控制源和目的地址寄存器的递增，在源和目的地之间的DMA传输期间进行数据压缩或解压缩公开(公告)号：US06385670B1
公开(公告)日：2002-05-07
申请号：US09088133
申请日：1998-06-01
IPC分类号： G06F1314
CPC分类号： G06F13/28
摘要： A microcontroller includes a direct memory access unit that compresses and decompresses data and transfers from one block of memory to another. Specifically, word size data can be read, one byte discarded, and stored as consecutive, byte size data. This can be used in conjunction with an extended read and extended write asynchronous serial port that stores status information along with data. Once the status information is processed, the status is stripped by performing the “compressive” DMA.
摘要翻译： 微控制器包括直接存储器访问单元，其压缩和解压缩数据并从一个存储器块传送到另一个存储器。 具体来说，可以读取字长数据，丢弃一个字节，并作为连续的字节大小数据存储。 这可以与扩展的读取和扩展写入异步串行端口一起使用，它将状态信息和数据一起存储。 处理状态信息后，通过执行“压缩”DMA来剥离状态。
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6.发明授权Microcontroller architecture and associated method providing for testing of an on-chip memory device 失效提供片上存储器件测试的微控制器架构和相关方法公开(公告)号：US06263460B1
公开(公告)日：2001-07-17
申请号：US09105779
申请日：1998-06-28
IPC分类号： G11C2900
CPC分类号： G11C29/48 , G11C11/41 , G11C29/1201 , G11C2207/104
摘要： A microcontroller architecture and an associated method are presented which provide for testing of an “on-chip” memory unit. The microcontroller includes a microcontroller core, the memory unit, a set of input/output (I/O) pads, and an input/output (I/O) pad interface unit, all formed upon a single monolithic semiconductor substrate. The microcontroller core executes instructions and generates data. The memory unit is coupled to the microcontroller core and stores data. The memory unit may include a common static random access memory (SRAM) device having multiple memory cells with load devices permitting static operation. A data latch within the memory unit samples retrieved data and provides the retrieved data to the microcontroller core. The data latch is responsive to a data latch control (DLC) signal produced by the I/O pad interface unit. The I/O pad interface unit receives a signal from one or more members of the set of I/O pads and generates the DLC signal in response to the signal. In a testing mode of the microcontroller, the DLC signal is asserted, and latching of retrieved data occurs on the next transition of a system clock cycle following assertion of the row select signal. Thus in the testing mode, the length of a time period between assertion of the row select signal and the latching of the retrieved data by the data latch is variable and dependent upon the duty cycle of the system clock signal.
摘要翻译： 提出了一种微控制器架构和相关方法，其提供了对“片上”存储器单元的测试。 微控制器包括微控制器核心，存储器单元，一组输入/输出（I / O）焊盘以及全部形成在单个单片半导体衬底上的输入/输出（I / O）焊盘接口单元。 微控制器内核执行指令并生成数据。 存储器单元耦合到微控制器核心并存储数据。 存储器单元可以包括具有多个存储器单元的公共静态随机存取存储器（SRAM）器件，其中负载器件允许静态操作。 存储器单元内的数据锁存器对检索的数据进行采样并将检索的数据提供给微控制器核心。 数据锁存器响应由I / O焊盘接口单元产生的数据锁存控制（DLC）信号。 I / O焊盘接口单元从一组I / O焊盘的一个或多个成员接收信号，并响应该信号产生DLC信号。 在微控制器的测试模式下，DLC信号被断言，并且检索到的数据的锁存发生在行选择信号的断言之后的系统时钟周期的下一个转换中。 因此，在测试模式中，行选择信号的断言和数据锁存器检索的数据的锁存之间的时间长度是可变的并且取决于系统时钟信号的占空比。
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