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1.发明授权Prevention of head of line blocking in a multi-rate switched Fibre Channel loop attached system 有权在多速率交换光纤通道环路连接系统中防止线路阻塞的头部公开(公告)号：US07586850B2
公开(公告)日：2009-09-08
申请号：US11064550
申请日：2005-02-23
IPC分类号： H04L12/26
CPC分类号： H04L49/508 , H04L49/357
摘要： A method is disclosed for maintaining a table of recent accesses for each port for use in predicting whether a request for data from a source device is likely to be sent to a high speed or low speed destination device. The table of recent accesses lists every source device attached to that port and the speed of the destination device with the most recent access to each source device. When an OPN primitive is received at the source port, the source device is identified and used with the table of recent accesses to predict whether the destination device is likely to be high speed or low speed, and ultimately whether to send data from the source device or reject the request.
摘要翻译： 公开了一种用于维护每个端口的最近访问的表的方法，用于预测来自源设备的数据的请求是否可能被发送到高速或低速目的地设备。 最近访问表列出了连接到该端口的每个源设备和目标设备的速度，最近访问每个源设备。 当在源端口接收到OPN原语时，源设备被识别并与最近的访问表一起使用以预测目的地设备是否可能是高速或低速的，并且最终是否从源设备发送数据 或拒绝该请求。
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公开(公告)号：US07876713B2
公开(公告)日：2011-01-25
申请号：US11823995
申请日：2007-06-29
摘要： The attaching of labels to an OPEN frame and applying label switched routing to SAS expanders is disclosed to eliminate the need for large routing tables in SAS networks. A label stack is inserted into the OPEN frame by the initiator, prior to the OPEN frame being transmitted. Each label contains the egress port for a SAS expander in the transmit path. Each SAS expander to be participating in the connection reads the labels to determine the egress port to connect to and through which data is to be sent. The SAS expander marks its label invalid or discards it and forwards the OPEN frame to the egress port where the next SAS expander will look for the first valid label. The process repeats until the OPEN frame reaches the edge device, at which time all labels are discarded and the OPEN frame is forwarded to the end device.
摘要翻译： 公开了将标签附加到OPEN帧并且将标签交换路由应用于SAS扩展器以消除对SAS网络中的大路由表的需要。 在发送OPEN帧之前，发起者将标签堆栈插入OPEN帧。 每个标签包含发送路径中SAS扩展器的出口端口。 要参与连接的每个SAS扩展器都会读取标签，以确定要连接的出口端口以及要发送的数据。 SAS扩展器标记其标签无效或丢弃它，并将OPEN帧转发到出口端口，下一个SAS扩展器将寻找第一个有效标签。 该过程重复，直到OPEN帧到达边缘设备，此时所有标签都被丢弃，OPEN帧被转发到终端设备。
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3.发明授权Controlling device access fairness in switched fibre channel fabric loop attachment systems 有权在交换光纤通道结构环路连接系统中控制设备访问公平性公开(公告)号：US07813360B2
公开(公告)日：2010-10-12
申请号：US11044444
申请日：2005-01-26
IPC分类号： H04L12/28 , H04L12/56 , G01R31/08 , G06F11/00 , G08C15/00 , H04J1/16 , H04J3/14 , H04L1/00 , H04L12/26
CPC分类号： H04L49/357 , H04L49/15 , H04L49/3009 , H04L49/503
摘要： Embodiments of the present invention are directed to controlling device access fairness in frame-based switches by automatically and continuously counting the number of actively communicating devices connected to each port and the type of devices connected to each port, and adjusting fairness accordingly. During a sampling window, the number of active devices and the type of devices connected to each port is determined. At the start of each fairness window, a weighted number of slots are assigned to each port based on the number of active devices connected to each port and the type of devices connected to that port. Within a single fairness window, each port is able to provide device accesses to the frame-based switch in accordance with the number of slots assigned to that port.
摘要翻译： 本发明的实施例涉及通过自动连续计数连接到每个端口的主动通信设备的数量和连接到每个端口的设备的类型，并相应地调整公平性来控制基于帧的交换机中的设备接入公平性。 在采样窗口期间，确定有源设备的数量和连接到每个端口的设备类型。 在每个公平窗口的开始，基于连接到每个端口的活动设备的数量和连接到该端口的设备的类型，向每个端口分配加权的时隙数。 在单个公平窗口中，每个端口能够根据分配给该端口的时隙数量向基于帧的交换机提供设备访问。
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公开(公告)号：US20090006697A1
公开(公告)日：2009-01-01
申请号：US11823995
申请日：2007-06-29
IPC分类号： G06F13/40
摘要： The attaching of labels to an OPEN frame and applying label switched routing to SAS expanders is disclosed to eliminate the need for large routing tables in SAS networks. A label stack is inserted into the OPEN frame by the initiator, prior to the OPEN frame being transmitted. Each label contains the egress port for a SAS expander in the transmit path. Each SAS expander to be participating in the connection reads the labels to determine the egress port to connect to and through which data is to be sent. The SAS expander marks its label invalid or discards it and forwards the OPEN frame to the egress port where the next SAS expander will look for the first valid label. The process repeats until the OPEN frame reaches the edge device, at which time all labels are discarded and the OPEN frame is forwarded to the end device.
摘要翻译： 公开了将标签附加到OPEN帧并且将标签交换路由应用于SAS扩展器以消除对SAS网络中的大路由表的需要。 在发送OPEN帧之前，发起者将标签堆栈插入OPEN帧。 每个标签包含发送路径中SAS扩展器的出口端口。 要参与连接的每个SAS扩展器都会读取标签，以确定要连接的出口端口以及要发送的数据。 SAS扩展器标记其标签无效或丢弃它，并将OPEN帧转发到出口端口，下一个SAS扩展器将寻找第一个有效标签。 该过程重复，直到OPEN帧到达边缘设备，此时所有标签都被丢弃，OPEN帧被转发到终端设备。
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公开(公告)号：US07743178B2
公开(公告)日：2010-06-22
申请号：US11104341
申请日：2005-04-11
申请人： Bruce Gregory Warren , Curtis Edward Nottberg , Carl Joseph Mies , Kevin Dale Bowman , Noumaan Ahmed Shah , Gary Lynn Franco
发明人： Bruce Gregory Warren , Curtis Edward Nottberg , Carl Joseph Mies , Kevin Dale Bowman , Noumaan Ahmed Shah , Gary Lynn Franco
IPC分类号： H04L5/00
CPC分类号： G06F3/0661 , G06F3/0607 , G06F3/067 , H04L67/1097 , H04L69/08
摘要： A system for enabling SATA drives to be utilized in FC SANs is disclosed. To send data to a SATA drive over a FC SAN, a host sends SCSI commands encapsulated in FC frames over a standard FC link to a Fibre Channel Attached SATA Tunneling (FAST) RAID controller, where the SCSI commands are de-encapsulated from the FC frames and translated to SATA FISs. The SATA FISs are thereafter encapsulated into FC frames. The IOC that performs these functions is referred to as a FAST IOC. The SATA-encapsulated FC frames are sent to multiple disk drive enclosures over another standard FC link. The FC frames are de-encapsulated by FAST switches in disk drive enclosures to retrieve the SATA FISs, and the SATA FISs are sent to the SATA drives over a SATA connection.
摘要翻译： 公开了一种用于在FC SAN中使用SATA驱动器的系统。 要通过FC SAN将数据发送到SATA驱动器，主机将通过标准FC链路封装在FC帧中的SCSI命令发送到光纤通道附加SATA隧道（FAST）RAID控制器，其中SCSI命令从FC中解封装 框架并转换为SATA FIS。 然后将SATA FIS封装到FC帧中。 执行这些功能的IOC被称为FAST IOC。 SATA封装的FC帧通过另一个标准FC链路发送到多个磁盘驱动器机箱。 FC框架由磁盘驱动器机箱中的FAST开关解封装，以检索SATA FIS，SATA FIS通过SATA连接发送到SATA驱动器。
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公开(公告)号：US07853741B2
公开(公告)日：2010-12-14
申请号：US11104230
申请日：2005-04-11
IPC分类号： G06F3/00
CPC分类号： H04L67/1097 , G06F3/0604 , G06F3/0607 , G06F3/0661 , G06F3/067 , H04L67/16 , H04L69/08
摘要： A system for enabling SATA drives to be utilized in FC SANs is disclosed. To send SATA FISs to a SATA drive over a FC SAN, a host sends SCSI commands encapsulated in FC frames over a standard FC link to a Fiber Channel Attached SATA Tunneling (FAST) RAID controller, where the SCSI commands are de-encapsulated from the FC frames and translated to SATA FISs. The SATA FISs are thereafter encapsulated into FC frames. The IOC that performs these functions is referred to as a FAST IOC. The SATA-encapsulated FC frames are sent to multiple disk drive enclosures over another standard FC link. The FC frames are de-encapsulated by FAST switches in disk drive enclosures to retrieve the SATA FISs, and the SATA FISs are sent to the SATA drives over a SATA connection.
摘要翻译： 公开了一种用于在FC SAN中使用SATA驱动器的系统。 要通过FC SAN将SATA FIS发送到SATA驱动器，主机通过标准FC链路将FC封装在FC帧中的SCSI命令发送到光纤通道附加SATA隧道（FAST）RAID控制器，其中SCSI命令从 FC帧并转换为SATA FIS。 然后将SATA FIS封装到FC帧中。 执行这些功能的IOC被称为FAST IOC。 SATA封装的FC帧通过另一个标准FC链路发送到多个磁盘驱动器机箱。 FC框架由磁盘驱动器机箱中的FAST开关解封装，以检索SATA FIS，SATA FIS通过SATA连接发送到SATA驱动器。
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公开(公告)号：US09065742B2
公开(公告)日：2015-06-23
申请号：US11966922
申请日：2007-12-28
CPC分类号： H04L43/12 , H04L43/18 , H04L67/1097
摘要： Snooping in SAS expander networks is disclosed. Ports in a SAS expander may include snoop circuitry and a snoop tap which allows snoop data to be diverted for snooping prior to any significant transformation of the traffic by the regular port logic. Furthermore, the snoop circuitry can receive OOB signaling and convert it to K characters for transmission through the SAS network and subsequent analysis by a protocol analyzer. The ports and cascades in the expander network can be configured to create snoop paths to enable snoop data to be passed through the network to locations where a protocol analyzer can be easily attached. With SAS snoop ports, there is no disruption to the system. Because only a copy of the data is routed to the analyzer, there is no change to the original signal path and latency is identical with or without the analyzer.
摘要翻译： 披露了SAS扩展器网络中的侦听。 在SAS扩展器中的端口可以包括窥探电路和窥探抽头，其允许窥探数据被转移以在通过常规端口逻辑的业务的任何重大变换之前进行窥探。 此外，监听电路可以接收OOB信令，并将其转换为K字符，以便通过SAS网络进行传输，然后由协议分析器进行后续分析。 扩展器网络中的端口和级联可以配置为创建窥探路径，以使窥探数据能够通过网络传递到协议分析器可以轻松连接的位置。 使用SAS snoop端口，系统不会中断。 因为只有数据的副本才能路由到分析仪，所以原始信号路径没有改变，延迟与分析仪是否相同。
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公开(公告)号：US20090240986A1
公开(公告)日：2009-09-24
申请号：US12054323
申请日：2008-03-24
IPC分类号： G06F11/28
CPC分类号： G06F11/261 , G06F11/263 , G06F11/3696
摘要： Embodiments of the invention enable error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test.
摘要翻译： 本发明的实施例使得能够进行系统验证的误差仿真。 可以通过修改呈现给处理器的数据以及产生与ASIC硬件中修改的数据一致的中断来模拟错误。 修改逻辑可以被添加到ASIC，因此当微处理器尝试读取特定的地址时，修改逻辑可以屏蔽被请求地址返回的一个或多个数据位。 地址，位掩码和力值数据可以存储在寄存器中，以确定可以修改哪个地址，要修改的位位置，以及应该改变位位置的值。 然后，选择逻辑可以确定来自修改逻辑的数据或来自附加设备的未修改值是否应发送到ASIC接口和微处理器。 也可以使用定时器将设置与测试分离。
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公开(公告)号：US09400616B2
公开(公告)日：2016-07-26
申请号：US11395648
申请日：2006-03-30
申请人： Carl Joseph Mies , Bruce Gregory Warren , William Patrick Goodwin , Lawrence Toshiyuki Shiihara
发明人： Carl Joseph Mies , Bruce Gregory Warren , William Patrick Goodwin , Lawrence Toshiyuki Shiihara
IPC分类号： G06F13/372 , G06F3/06
CPC分类号： G06F3/0659 , G06F3/0614 , G06F3/0658 , G06F3/067
摘要： Controlling accesses to target devices such as disk drives by modifying the duty cycle profile of those devices to improve device reliability is disclosed. The utilization of a target device is monitored, and if a device is being overused, that device is given a rest period by reserving it for a special initiator that does not send any commands to the device for a certain period of time. This reduced utilization has the effect of increasing the reliability of the target device. This period of time also adds a delay to the processing of commands for the target device being overutilized so that the device becomes less responsive. This performance penalty creates pressure on system administrators to reduce the number of commands sent to that target device and/or move data to proper devices (that can handle the high number of accesses).
摘要翻译： 公开了通过修改这些设备的占空比轮廓以提高设备可靠性来控制对目标设备（例如磁盘驱动器）的访问。 对目标设备的使用情况进行监控，如果设备被过度使用，该设备将通过为特定启动器预留一段休息时间，该启动器不会向设备发送任何命令一段时间。 这种降低的利用率具有提高目标设备的可靠性的效果。 这个时间段也增加了对目标设备被过度利用的命令的处理的延迟，使得该设备的响应性降低。 这种性能损失会给系统管理员造成压力，以减少发送到该目标设备的命令数量和/或将数据移动到适当的设备（可以处理大量访问）。
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公开(公告)号：US08522080B2
公开(公告)日：2013-08-27
申请号：US12054323
申请日：2008-03-24
IPC分类号： G06F11/00
CPC分类号： G06F11/261 , G06F11/263 , G06F11/3696
摘要： This invention relates to error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test.
摘要翻译： 本发明涉及系统验证的误差仿真。 可以通过修改呈现给处理器的数据以及产生与ASIC硬件中修改的数据一致的中断来模拟错误。 修改逻辑可以被添加到ASIC，因此当微处理器尝试读取特定的地址时，修改逻辑可以屏蔽被请求地址返回的一个或多个数据位。 地址，位掩码和力值数据可以存储在寄存器中，以确定可以修改哪个地址，要修改的位位置，以及应该改变位位置的值。 然后，选择逻辑可以确定来自修改逻辑的数据或来自附加设备的未修改值是否应发送到ASIC接口和微处理器。 也可以使用定时器将设置与测试分离。
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