公开(公告)号：US07096144B1

公开(公告)日：2006-08-22

申请号：US10913907

申请日：2004-08-09

申请人： Bruce L. Bateman

发明人： Bruce L. Bateman

IPC分类号： G01M19/00 ,  G06F19/00

CPC分类号： G01R31/31725

摘要： A sampling circuit for testing an integrated circuit receives several signals from points of interest in the integrated circuit, digitizes them, and determines whether the digitized signal is above or below a threshold. By sampling the signal at different phases of a system clock signal, a determination can be made of when during the system clock signal the signal at a point of interest changed state. Circuits are provided for making minimal impact on the circuit being observed. Circuits are also provided for clocking the observed signal so that it can be compared to other observed signals.

摘要翻译： 用于测试集成电路的采样电路从集成电路中的兴趣点接收多个信号，对它们进行数字化，并确定数字化信号是高于还是低于阈值。 通过对系统时钟信号的不同相位处的信号进行采样，可以确定在系统时钟信号期间何时在兴趣点改变状态的信号。 提供电路以对所观察的电路产生最小的影响。 还提供电路用于对所观察的信号进行计时，以便将其与其他观测信号进行比较。

公开(公告)号：US5535166A

公开(公告)日：1996-07-09

申请号：US280350

申请日：1994-07-25

申请人： Bruce L. Bateman

发明人： Bruce L. Bateman

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C7/02

CPC分类号： G11C5/143 ,  G11C7/062

摘要： A circuit for isolating an interconnect line from unwanted input signal voltage levels is described. One implementation of the circuit includes a transmission gate coupled in series between an input signal and an interconnect line having its gate coupled to the output of an inverter and the input of the inverter coupled to the input signal. The inverter senses the input signal and when it sense voltages that are either too high or low, the isolation circuit decouples the input signal from the interconnect line such that the input signal can transition independently with respect to the voltage levels on the interconnect line.

摘要翻译： 描述了用于将互连线与不需要的输入信号电压电平隔离的电路。 该电路的一个实施方式包括串联连接在输入信号和互连线之间的传输门，其互连线与其反相器的输出耦合，并且反相器的输入耦合到输入信号。 逆变器检测输入信号，当检测到过高或过低的电压时，隔离电路将输入信号与互连线分离，使得输入信号可以相对于互连线上的电压电平独立地转变。

公开(公告)号：US4636983A

公开(公告)日：1987-01-13

申请号：US683062

申请日：1984-12-20

申请人： Kenneth E. Young ,  Bruce L. Bateman

发明人： Kenneth E. Young ,  Bruce L. Bateman

IPC分类号： H03K19/00 ,  G11C7/12 ,  H03K19/0948 ,  G11C11/40

CPC分类号： G11C7/12

摘要： A current limiting, process compensating circuit for CMOS memory arrays is provided. A dual transistor bias circuit is connected to each of a pair of columns of the array with a four transistor voltage reference circuit having its output connected to the gates of the active P-channel transistor of each bias circuit. A first P-channel transistor of the voltage reference circuit is sized to be less than the P-channel transistor of the bias circuit and the other three N-channel transistors are sized to be the same as the second transistor of the bias circuit and the two transistors of each memory cell in the array. As supply voltage to the array moves up or down making more or less current available, the combined circuit maintains nearly constant current on the first transistor of each bias circuit while compensating for process variation.

摘要翻译： 提供了一种用于CMOS存储器阵列的限流工艺补偿电路。 双晶体管偏置电路通过具有连接到每个偏置电路的有源P沟道晶体管的栅极的四个晶体管电压参考电路连接到阵列的一对列中的每一个。 电压参考电路的第一P沟道晶体管的尺寸被设计成小于偏置电路的P沟道晶体管，而另外三个N沟道晶体管的尺寸被设计成与偏置电路的第二晶体管相同， 阵列中每个存储单元的两个晶体管。 随着阵列的电源电压向上或向下移动或多或少的电流可用，组合电路在每个偏置电路的第一晶体管上保持几乎恒定的电流，同时补偿工艺变化。