公开(公告)号：US4945548A

公开(公告)日：1990-07-31

申请号：US257907

申请日：1988-10-14

申请人： John R. Iannarone ,  Bruce W. Thompson

发明人： John R. Iannarone ,  Bruce W. Thompson

IPC分类号： G06F5/10 ,  G06F5/14 ,  H04J3/06

CPC分类号： G06F5/14 ,  G06F2205/102 ,  H04L2007/045

摘要： A parallel asynchronous elasticity buffer. Selection of the address of a storage element for writing or reading of data is provided by asynchronous input and output pointers implemented using circular gray code counters. The buffer is initialized once during transmission of each frame of data so that the pointers do not select the same storage element for writing and reading at the same time. Write overflow or read underrun of a storage element is detected before any data corruption can occur by comparing the input and output pointers. An error condition is detected if the input and output pointers overlap for a threshold period, which can be shorter than the period required for writing or reading of a multibit data unit to or from the buffer. The overlap time period is determined by comparing the pointers at one or more sampling times corresponding to selected phases of a clock signal.

摘要翻译： 并行异步弹性缓冲器。 选择用于写入或读取数据的存储元件的地址由使用循环灰度代码计数器实现的异步输入和输出指针提供。 在每帧数据的传输期间，缓冲器被初始化一次，使得指针不会同时选择用于写入和读取的相同存储元件。 在通过比较输入和输出指针发生任何数据损坏之前，检测到存储元件的写入溢出或读取欠载。 如果输入和输出指针重叠一个阈值周期，那么可以检测出错误条件，该阈值周期可能短于向缓冲器写入或读取多位数据单元所需的周期。 通过在对应于时钟信号的所选相位的一个或多个采样时间比较指针来确定重叠时间段。

公开(公告)号：US06645410B2

公开(公告)日：2003-11-11

申请号：US10150684

申请日：2002-05-17

申请人： Bruce W. Thompson

发明人： Bruce W. Thompson

IPC分类号： B29C4706

CPC分类号： B29C47/065 ,  B29C47/0023 ,  B29C47/0026 ,  B29C47/0028 ,  B29C47/003 ,  B29C47/0052 ,  B29C47/882 ,  B29C47/8895 ,  B29C47/903 ,  B29C47/905 ,  B29C47/908 ,  B29L2023/22 ,  B29L2031/601 ,  B29L2031/603 ,  B29L2031/605

摘要： A manufacturing apparatus and method for multiple containment tubing produces continuous, nested tubing, or one tube within another tube, without having to fix the space between the tubes or position them concentrically. Consequently the tubing is very flexible and with uniform wall thickness. Moreover, because the inner surface of the outer tube and the outer surface of the inner tube are ribless, these kinds of features cannot interfere with the bending and twisting and the operation of the tubes comprising the tubing. The space between the tubes, or free space, has sufficient volume to contain a range of contents of the inner tube, as a safety containment device, if the inner tube ruptures, cracks, or otherwise breaks.

公开(公告)号：US06310882B1

公开(公告)日：2001-10-30

申请号：US09238880

申请日：1999-01-27

申请人： Gary D. Lorenz ,  Bruce W. Thompson ,  Harsh Kapoor ,  Charles R. Weaver ,  Brian J. Myrick

发明人： Gary D. Lorenz ,  Bruce W. Thompson ,  Harsh Kapoor ,  Charles R. Weaver ,  Brian J. Myrick

IPC分类号： H04L1246

CPC分类号： H04L45/742 ,  H04L49/351 ,  H04L49/354 ,  H04L49/357

摘要： A switching architecture for very high data rates which is placed between a port connecting to a fiber optic gigabit ethernet link and a two Gbit/sec backplane of a concentrator. A port connects to the link for both receiving and transmitting data packets from and to the link. A first FTE receives a data packet from the port, and analyzes the data packet to determine if the data packet should be forwarded to the backplane of the concentrator. If the data packet is to be forwarded, the first FTE sends the data packet to a backplane connection for connecting to the backplane of the network concentrator. A second FTE is connected to the backplane connection. The second FTE receives a data packet from the backplane connection, and analyzes the data packet in a manner similar to the first FTE to determine if a packet should be forwarded to the port. The process of the second FTE with regard to the data packets is substantially similar to the process of the first FTE, except that it is determined whether or not the data packets from the backplane should be forwarded to the port. This switch architecture therefore uses separate transmit and receive channels with independent forwarding tables. The first and second FTE's can be substantially identical, and are preferably switch engine ASIC's (Application Specific Integrated Circuit) designed for a lower data rate.

摘要翻译： 用于非常高数据速率的交换架构，放置在连接到光纤千兆以太网链路的端口和集中器的两Gbit /秒背板之间。 端口连接到链路，用于从链路接收和发送数据包。 第一个FTE从端口接收数据包，并分析数据包以确定数据包是否应该转发到集中器的背板。 如果要转发数据包，则第一个FTE将数据包发送到背板连接，以连接到网络集线器的背板。 第二个FTE连接到背板连接。 第二FTE从背板连接接收数据包，并以类似于第一FTE的方式分析数据包，以确定是否将数据包转发到端口。 关于数据分组的第二FTE的处理与第一FTE的处理基本相似，除了确定来自背板的数据分组是否应转发到端口。 因此，该交换架构使用具有独立转发表的单独的发送和接收信道。 第一和第二FTE可以是基本相同的，并且优选地被设计用于较低数据速率的开关引擎ASIC（专用集成电路）。