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公开(公告)号：US4761780A
公开(公告)日：1988-08-02
申请号：US945079
申请日：1986-12-22
CPC分类号： H04L12/5601 , H04L49/106 , H04L49/1561 , H04L49/255 , H04L2012/5651 , H04L2012/5681
摘要： A mechanism is disclosed for resolving conflicts between input ports of a Batcher-Banyan Packet switching network that wish to transmit data packets to the same output port during a particular packet switch cycle. The input ports of the Batcher-Banyon network are connected in a serial ring. Bit positions on the ring represent output ports. Each input port having a data packet to transmit to a particular output port may reserve that output port before the start of the next Batcher-Banyan packet switch cycle by writing a "1" in the ring bit position corresponding to the output port to which the data packet is addressed. If the particular output port has already been reserved by another input port, the data packet is buffered.
摘要翻译： 公开了一种用于解决在特定分组交换周期期间希望将数据分组发送到同一输出端口的分组器 - 悦榕分组交换网络的输入端口之间的冲突的机制。 Batcher-Banyon网络的输入端口连接在一个串行环上。 环上的位位表示输出端口。 具有要发送到特定输出端口的数据分组的每个输入端口可以在下一个分批器 - 榕树分组交换周期的开始之前将该输出端口预留在对应于输出端口的环位位置中的“1” 数据包被寻址。 如果特定的输出端口已被另一个输入端口保留，则数据包被缓冲。
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公开(公告)号：US5043980A
公开(公告)日：1991-08-27
申请号：US432921
申请日：1989-11-07
CPC分类号： H04L12/5601 , H04L49/106 , H04L49/1561 , H04L49/1592 , H04L49/405 , H04Q3/68 , H04L2012/5609
摘要： A cell for use in a packet switching network. The cell comprises an input for receiving a packet including a destination address and first and second outputs. The cell includes a selection circuit for connecting the input with the first output or the second output depending on whether a specific bit occupying a predetermined position in the packet address is a logic "1" or a logic "0". Illustratively, the specific bit is the first bit after a start bit of the packer and each of the cells includes means for rotating the specific bit to the end of the address. This is especially useful for implementing a banyan network wherein the k.sup.th column of cells the routing decision is based on the k.sup.th most significant bit of the address, as the address bit rotation mechanism can be used to ensure that the first bit after the start bit of a packet is the k.sup.th most significant address bit. Preferably, each of the cells may be disabled in response to a disabling signal so that the input is connected to the first or second output independently of the logic value of the specific bit. This permits a packet switching network to be formed from interconnected horizontal and vertical stacks of chips wherein selected cells are disabled.
摘要翻译： 用于分组交换网络的小区。 小区包括用于接收包含目的地地址和第一和第二输出的分组的输入。 单元包括用于将输入与第一输出或第二输出连接的选择电路，这取决于分组地址中占用预定位置的特定位是逻辑“1”还是逻辑“0”。 说明性地，特定位是封隔器的起始位之后的第一位，并且每个单元包括用于将特定位旋转到地址的末尾的装置。 这对于实现榕树网络尤其有用，其中第k列小区的路由决定是基于地址的第k个最高有效位，因为地址比特旋转机制可以用于确保起始位之后的第一比特 一个数据包是第k个最重要的地址位。 优选地，每个单元可以响应于禁用信号被禁用，使得输入与特定位的逻辑值无关地连接到第一或第二输出。 这允许分组交换网络由互连的水平和垂直堆栈的芯片形成，其中选择的小区被禁用。
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公开(公告)号：US4910730A
公开(公告)日：1990-03-20
申请号：US167790
申请日：1988-03-14
CPC分类号： H04L12/5601 , H04L49/106 , H04L49/1561 , H04L49/1592 , H04L49/255 , H04L49/405 , H04Q3/68
摘要： A Batcher-banyan network which may be implemented using only two different IC chip designs is disclosed. The chips comprising the Batcher banyan network are arranged in adjacent horizontal and vertical stacks to minimize the lengths of electrical conductors connecting the chips.
摘要翻译： 公开了可以使用两个不同的IC芯片设计来实现的分组器 - 榕树网络。 包括Batcher榕树网络的芯片布置在相邻的水平和垂直堆叠中，以使连接芯片的电导体的长度最小化。
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