公开(公告)号：US07507994B2

公开(公告)日：2009-03-24

申请号：US11625694

申请日：2007-01-22

申请人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Hao ,  Jong-Soo Yoon ,  Doug-Gyu Kim

发明人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Hao ,  Jong-Soo Yoon ,  Doug-Gyu Kim

IPC分类号： H01L29/04

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  G02F2001/136272 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765 ,  Y10S438/949

摘要： A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad.

摘要翻译： 包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘， 以及在基板上的栅电极。 此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。 依次形成栅极绝缘层，半导体层和欧姆接触层。 导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。

公开(公告)号：US07176496B2

公开(公告)日：2007-02-13

申请号：US11080612

申请日：2005-03-16

申请人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Hao ,  Jong-Soo Yoon ,  Dong-Gyu Kim

发明人： Bum-Ki Baek ,  Mun-Pyo Hong ,  Jang-Soo Kim ,  Sung-Wook Hao ,  Jong-Soo Yoon ,  Dong-Gyu Kim

IPC分类号： H01L29/04 ,  H01L29/15 ,  H01L31/36

CPC分类号： G02F1/13458 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136236 ,  G02F2001/136272 ,  G02F2001/13629 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765 ,  Y10S438/949

摘要： A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad. Next, a passivation layer is deposited and patterned to form contact holes respectively exposing the drain electrode, the gate pad, and the data pad. At this time, the contact hole on the gate pad only exposes the lower layer of the gate pad, and the gate insulating layer and the passivation layer completely cover the upper layer of the gate pad. Next, indium tin oxide is deposited and patterned to form a pixel electrode, a redundant gate pad, and a redundant data pad respectively connected to the pixel electrode, the gate pad, and the data pad.

摘要翻译： 包括由诸如铬，钼和钼合金的难熔金属制成的下层和由铝或铝合金制成的上层的导电层被沉积和图案化以形成包括栅极线，栅极焊盘， 以及在基板上的栅电极。 此时，根据作为蚀刻掩模的位置，使用具有不同厚度的光致抗蚀剂图案去除栅极焊盘的上层。 依次形成栅极绝缘层，半导体层和欧姆接触层。 导电材料被沉积并图案化以形成包括数据线，源电极，漏电极和数据焊盘的数据线。 接下来，沉积并图案化钝化层以形成分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。 此时，栅极焊盘上的接触孔仅暴露栅极焊盘的下层，栅极绝缘层和钝化层完全覆盖栅极焊盘的上层。 接下来，沉积和图案化氧化铟锡以形成分别连接到像素电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。