Semiconductor memory device and test method of the same
    1.
    发明授权
    Semiconductor memory device and test method of the same 有权
    半导体存储器件及其测试方法相同

    公开(公告)号:US09508453B2

    公开(公告)日:2016-11-29

    申请号:US13494492

    申请日:2012-06-12

    CPC classification number: G11C29/24 G11C15/00 G11C16/20

    Abstract: A semiconductor memory device includes a normal data storage block configured to store a normal data, a setup data storage block for storing a setup data including at least two duplicate data, an access unit configured to access the normal data of the normal data storage block or the setup data of the setup data storage block, a first transfer unit configured to transfer the setup data accessed by the access unit, a data decision unit configured to determine a correct data based on the setup data transferred by the first transfer unit, a second transfer unit configured to transfer the normal data accessed by the access unit, and a data output unit configured to output the setup data transferred by the first transfer unit or the normal data transferred by the second transfer unit to the outside of the semiconductor memory device in response to a control signal.

    Abstract translation: 一种半导体存储装置,包括被配置为存储正常数据的正常数据存储块,用于存储包括至少两个重复数据的建立数据的建立数据存储块,被配置为访问正常数据存储块的正常数据的访问单元, 设置数据存储块的设置数据,被配置为传送由访问单元访问的设置数据的第一传送单元,被配置为基于由第一传送单元传送的设置数据来确定正确数据的数据判定单元,第二传送单元 传送单元,被配置为传送由访问单元访问的正常数据;以及数据输出单元,被配置为将由第一传送单元传送的设置数据或由第二传送单元传送的正常数据输出到半导体存储设备的外部 对控制信号的响应。

    SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD OF THE SAME
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD OF THE SAME 有权
    半导体存储器件及其测试方法

    公开(公告)号:US20130166959A1

    公开(公告)日:2013-06-27

    申请号:US13494492

    申请日:2012-06-12

    CPC classification number: G11C29/24 G11C15/00 G11C16/20

    Abstract: A semiconductor memory device includes a normal data storage block configured to store a normal data, a setup data storage block for storing a setup data including at least two duplicate data, an access unit configured to access the normal data of the normal data storage block or the setup data of the setup data storage block, a first transfer unit configured to transfer the setup data accessed by the access unit, a data decision unit configured to determine a correct data based on the setup data transferred by the first transfer unit, a second transfer unit configured to transfer the normal data accessed by the access unit, and a data output unit configured to output the setup data transferred by the first transfer unit or the normal data transferred by the second transfer unit to the outside of the semiconductor memory device in response to a control signal.

    Abstract translation: 一种半导体存储装置,包括被配置为存储正常数据的正常数据存储块,用于存储包括至少两个重复数据的建立数据的建立数据存储块,被配置为访问正常数据存储块的正常数据的访问单元, 设置数据存储块的设置数据,被配置为传送由访问单元访问的设置数据的第一传送单元,被配置为基于由第一传送单元传送的设置数据来确定正确数据的数据判定单元,第二传送单元 传送单元,被配置为传送由访问单元访问的正常数据;以及数据输出单元,被配置为将由第一传送单元传送的设置数据或由第二传送单元传送的正常数据输出到半导体存储设备的外部 对控制信号的响应。

    Non-volatile memory device and method of programming in the same
    3.
    发明授权
    Non-volatile memory device and method of programming in the same 失效
    非易失性存储器件和编程方法相同

    公开(公告)号:US07701766B2

    公开(公告)日:2010-04-20

    申请号:US11949650

    申请日:2007-12-03

    Applicant: Byoung-In Joo

    Inventor: Byoung-In Joo

    CPC classification number: G11C16/10 G11C16/3454 G11C2216/14

    Abstract: A non-volatile memory device according to one example embodiment of the present invention includes a page buffer configured to have a first register for receiving data and storing temporarily the received data to be inputted to a pair of first bit lines, a second register coupled selectively to the first register and for storing temporarily data to be inputted to a pair of second bit lines, and a third register for storing temporarily specific data in accordance with a level of the data stored in the first register; a first bit line selecting circuit configured to couple selectively a given bit line of the first bit lines to the first register; and a second bit line selecting circuit configured to couple selectively a certain bit line of the second bit lines to the second register.

    Abstract translation: 根据本发明的一个示例实施例的非易失性存储器件包括:页缓冲器,其被配置为具有用于接收数据的第一寄存器,并临时存储要输入到一对第一位线的接收数据;选择性地耦合的第二寄存器 到第一寄存器并临时存储要输入到一对第二位线的数据;以及第三寄存器,用于根据存储在第一寄存器中的数据的电平临时存储特定数据; 第一位线选择电路,被配置为将所述第一位线的给定位线选择性地耦合到所述第一寄存器; 以及第二位线选择电路,被配置为将第二位线的特定位线选择性地耦合到第二寄存器。

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