Abstract:
A semiconductor memory device includes a normal data storage block configured to store a normal data, a setup data storage block for storing a setup data including at least two duplicate data, an access unit configured to access the normal data of the normal data storage block or the setup data of the setup data storage block, a first transfer unit configured to transfer the setup data accessed by the access unit, a data decision unit configured to determine a correct data based on the setup data transferred by the first transfer unit, a second transfer unit configured to transfer the normal data accessed by the access unit, and a data output unit configured to output the setup data transferred by the first transfer unit or the normal data transferred by the second transfer unit to the outside of the semiconductor memory device in response to a control signal.
Abstract:
A semiconductor memory device includes a normal data storage block configured to store a normal data, a setup data storage block for storing a setup data including at least two duplicate data, an access unit configured to access the normal data of the normal data storage block or the setup data of the setup data storage block, a first transfer unit configured to transfer the setup data accessed by the access unit, a data decision unit configured to determine a correct data based on the setup data transferred by the first transfer unit, a second transfer unit configured to transfer the normal data accessed by the access unit, and a data output unit configured to output the setup data transferred by the first transfer unit or the normal data transferred by the second transfer unit to the outside of the semiconductor memory device in response to a control signal.
Abstract:
A non-volatile memory device according to one example embodiment of the present invention includes a page buffer configured to have a first register for receiving data and storing temporarily the received data to be inputted to a pair of first bit lines, a second register coupled selectively to the first register and for storing temporarily data to be inputted to a pair of second bit lines, and a third register for storing temporarily specific data in accordance with a level of the data stored in the first register; a first bit line selecting circuit configured to couple selectively a given bit line of the first bit lines to the first register; and a second bit line selecting circuit configured to couple selectively a certain bit line of the second bit lines to the second register.