公开(公告)号：US08873315B2

公开(公告)日：2014-10-28

申请号：US13615951

申请日：2012-09-14

申请人： Byoung In Joo

发明人： Byoung In Joo

IPC分类号： G11C16/06

CPC分类号： G11C11/5642 ,  G11C16/06 ,  G11C16/3454

摘要： The present disclosure relates to a semiconductor memory device and a method of operation the semiconductor memory device, which sets an encoding value by sequentially defining ranges used for recognizing distribution of memory cells based on a middle range and then performing a read operation in an order from the middle ranges to an outermost range, thereby capable of using infinite ranges for recognizing the distribution of the memory cells without addition of a circuit to an inside of the semiconductor memory device.

摘要翻译： 半导体存储器件和半导体存储器件的操作方法技术领域本公开涉及一种半导体存储器件和半导体存储器件的操作方法，该半导体存储器件通过依次定义用于识别基于中间范围的存储器单元的分配的范围来设置编码值，然后以从 中间范围到最外面的范围，从而能够使用无限范围来识别存储器单元的分布，而不向半导体存储器件的内部添加电路。

公开(公告)号：US07701766B2

公开(公告)日：2010-04-20

申请号：US11949650

申请日：2007-12-03

申请人： Byoung-In Joo

发明人： Byoung-In Joo

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C16/3454 ,  G11C2216/14

摘要： A non-volatile memory device according to one example embodiment of the present invention includes a page buffer configured to have a first register for receiving data and storing temporarily the received data to be inputted to a pair of first bit lines, a second register coupled selectively to the first register and for storing temporarily data to be inputted to a pair of second bit lines, and a third register for storing temporarily specific data in accordance with a level of the data stored in the first register; a first bit line selecting circuit configured to couple selectively a given bit line of the first bit lines to the first register; and a second bit line selecting circuit configured to couple selectively a certain bit line of the second bit lines to the second register.

摘要翻译： 根据本发明的一个示例实施例的非易失性存储器件包括：页缓冲器，其被配置为具有用于接收数据的第一寄存器，并临时存储要输入到一对第一位线的接收数据;选择性地耦合的第二寄存器 到第一寄存器并临时存储要输入到一对第二位线的数据;以及第三寄存器，用于根据存储在第一寄存器中的数据的电平临时存储特定数据; 第一位线选择电路，被配置为将所述第一位线的给定位线选择性地耦合到所述第一寄存器; 以及第二位线选择电路，被配置为将第二位线的特定位线选择性地耦合到第二寄存器。

公开(公告)号：US20080266961A1

公开(公告)日：2008-10-30

申请号：US11949650

申请日：2007-12-03

申请人： Byoung In JOO

发明人： Byoung In JOO

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C16/3454 ,  G11C2216/14

摘要： A non-volatile memory device according to one example embodiment of the present invention includes a page buffer configured to have a first register for receiving data and storing temporarily the received data to be inputted to a pair of first bit lines, a second register coupled selectively to the first register and for storing temporarily data to be inputted to a pair of second bit lines, and a third register for storing temporarily specific data in accordance with a level of the data stored in the first register; a first bit line selecting circuit configured to couple selectively a given bit line of the first bit lines to the first register; and a second bit line selecting circuit configured to couple selectively a certain bit line of the second bit lines to the second register.

摘要翻译： 根据本发明的一个示例实施例的非易失性存储器件包括：页缓冲器，其被配置为具有用于接收数据的第一寄存器，并临时存储要输入到一对第一位线的接收数据;选择性地耦合的第二寄存器 到第一寄存器并临时存储要输入到一对第二位线的数据;以及第三寄存器，用于根据存储在第一寄存器中的数据的电平临时存储特定数据; 第一位线选择电路，被配置为将所述第一位线的给定位线选择性地耦合到所述第一寄存器; 以及第二位线选择电路，被配置为将第二位线的特定位线选择性地耦合到第二寄存器。

公开(公告)号：US20140010008A1

公开(公告)日：2014-01-09

申请号：US13615951

申请日：2012-09-14

申请人： Byoung In JOO

发明人： Byoung In JOO

IPC分类号： G11C16/06

CPC分类号： G11C11/5642 ,  G11C16/06 ,  G11C16/3454

摘要： The present disclosure relates to a semiconductor memory device and a method of operation the semiconductor memory device, which sets an encoding value by sequentially defining ranges used for recognizing distribution of memory cells based on a middle range and then performing a read operation in an order from the middle ranges to an outermost range, thereby capable of using infinite ranges for recognizing the distribution of the memory cells without addition of a circuit to an inside of the semiconductor memory device.

摘要翻译： 半导体存储器件和半导体存储器件的操作方法技术领域本公开涉及一种半导体存储器件和半导体存储器件的操作方法，该半导体存储器件通过依次定义用于识别基于中间范围的存储器单元分布的范围来设置编码值，然后以从 中间范围到最外面的范围，从而能够使用无限范围来识别存储器单元的分布，而不向半导体存储器件的内部添加电路。

公开(公告)号：US07668030B2

公开(公告)日：2010-02-23

申请号：US12117703

申请日：2008-05-08

申请人： Byoung In Joo

发明人： Byoung In Joo

IPC分类号： G11C7/00

CPC分类号： G11C8/08 ,  G11C7/12

摘要： A method of operating a non-volatile memory device reduces a time for discharging a precharged voltage when a program operation or a read operation is performed, thereby decreasing a total operation time of the non-volatile memory device. The non-volatile memory device discharges a bit line and a word line using only a control signal without reading an algorithm block when a precharged voltage is discharged. The method of operating a non-volatile memory device includes detecting an operation command; generating algorithm blocks for generating an operation voltage, for precharging a bit line and a word line, and for performing a specific operation in accordance with the operation command; outputting a discharge enable control signal for the bit line and the word line; and reading an algorithm of turning off and discharging a voltage generating means for generating the operation voltage.

摘要翻译： 操作非易失性存储器件的方法在执行程序操作或读取操作时减少了放电预充电电压的时间，从而减少了非易失性存储器件的总操作时间。 当预充电电压放电时，非易失性存储器件仅使用控制信号放电位线和字线而不读取算法块。 操作非易失性存储装置的方法包括检测操作命令; 产生用于产生操作电压的算法块，用于对位线和字线进行预充电，并且用于根据操作命令执行特定操作; 输出位线和字线的放电使能控制信号; 以及读取关闭和放电用于产生操作电压的电压产生装置的算法。

公开(公告)号：US20130166959A1

公开(公告)日：2013-06-27

申请号：US13494492

申请日：2012-06-12

申请人： Byoung-In Joo ,  Chul-Woo Yang

发明人： Byoung-In Joo ,  Chul-Woo Yang

IPC分类号： G06F12/00 ,  G06F11/28

CPC分类号： G11C29/24 ,  G11C15/00 ,  G11C16/20

摘要： A semiconductor memory device includes a normal data storage block configured to store a normal data, a setup data storage block for storing a setup data including at least two duplicate data, an access unit configured to access the normal data of the normal data storage block or the setup data of the setup data storage block, a first transfer unit configured to transfer the setup data accessed by the access unit, a data decision unit configured to determine a correct data based on the setup data transferred by the first transfer unit, a second transfer unit configured to transfer the normal data accessed by the access unit, and a data output unit configured to output the setup data transferred by the first transfer unit or the normal data transferred by the second transfer unit to the outside of the semiconductor memory device in response to a control signal.

摘要翻译： 一种半导体存储装置，包括被配置为存储正常数据的正常数据存储块，用于存储包括至少两个重复数据的建立数据的建立数据存储块，被配置为访问正常数据存储块的正常数据的访问单元， 设置数据存储块的设置数据，被配置为传送由访问单元访问的设置数据的第一传送单元，被配置为基于由第一传送单元传送的设置数据来确定正确数据的数据判定单元，第二传送单元 传送单元，被配置为传送由访问单元访问的正常数据;以及数据输出单元，被配置为将由第一传送单元传送的设置数据或由第二传送单元传送的正常数据输出到半导体存储设备的外部 对控制信号的响应。

公开(公告)号：US08270219B2

公开(公告)日：2012-09-18

申请号：US12826936

申请日：2010-06-30

申请人： Byoung In Joo

发明人： Byoung In Joo

IPC分类号： G11C16/04

CPC分类号： G11C11/5642

摘要： A nonvolatile memory device is operated by receiving a dual plane read command for simultaneously reading first and second planes, each comprising memory cells, receiving an MSB read address for reading data stored in the memory cells, checking whether an MSB program operation has been performed on each of the first and second planes, and performing the read operation on the first and second planes according to a result of the check and outputting the read data.

摘要翻译： 通过接收双平面读取命令来操作非易失性存储器件，用于同时读取第一和第二平面，每个平面包括存储器单元，接收用于读取存储在存储器单元中的数据的MSB读取地址，检查是否执行了MSB编程操作 每个第一和第二平面，并且根据检查的结果对第一和第二平面执行读取操作并输出读取的数据。

公开(公告)号：US08228740B2

公开(公告)日：2012-07-24

申请号：US12814451

申请日：2010-06-12

申请人： Byoung In Joo

发明人： Byoung In Joo

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G06F11/1048 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2216/14

摘要： A nonvolatile memory device is operated by, inter alia, performing a program operation on memory cells belonging to a page selected from among a plurality of pages, performing a verification operation on the programmed memory cells, loading a start loop value of a fail bit count set to the selected page, from among start loop values of fail bit counts set to the respective pages, and if a loop value of the program operation is greater than or equal to the start loop value, counting a number of fail bits included in data of the programmed memory cells detected in the verification operation.

摘要翻译： 非易失性存储器件通过尤其对属于从多个页面中选择的页面的存储器单元执行编程操作来操作，对所编程的存储器单元执行验证操作，加载故障位计数的启动循环值 设置到所选择的页面，从设置到各个页面的故障位计数的起始循环值中，并且如果程序操作的循环值大于或等于起始循环值，则对包含在数据中的故障位数进行计数 在验证操作中检测到​​的编程存储器单元。

公开(公告)号：US20110158001A1

公开(公告)日：2011-06-30

申请号：US12982794

申请日：2010-12-30

申请人： Byoung In JOO

发明人： Byoung In JOO

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/10

摘要： A programming method for a nonvolatile memory device includes inputting least significant bit (LSB) data and most significant bit (MSB) data to each of different latches of a page buffer and in the state in which the LSB data and the MSB data have been inputted to the page buffer, performing a programming operation until threshold voltages of selected memory cells reach a target voltage on the basis of the LSB data and the MSB data.

摘要翻译： 用于非易失性存储器件的编程方法包括向页缓冲器的每个不同锁存器输入最低有效位（LSB）数据和最高有效位（MSB））数据，并且在LSB数据和MSB数据已被输入的状态 到页缓冲器，执行编程操作，直到所选存储单元的阈值电压基于LSB数据和MSB数据达到目标电压。

公开(公告)号：US20100332898A1

公开(公告)日：2010-12-30

申请号：US12826545

申请日：2010-06-29

申请人： Byoung In JOO

发明人： Byoung In JOO

IPC分类号： G06F12/16 ,  G06F11/14

CPC分类号： G06F11/1433 ,  G11C16/12

摘要： A nonvolatile memory device includes a plurality of memory blocks each configured to include a plurality of pages, a plurality of page buffers configured to correspond to the plurality of memory blocks and send copyback data, a controller configured to send the copyback data to a page buffer selected from among the page buffers, and a register configured to store an address of a page that has been failed, from among the pages, during a copyback program operation.

摘要翻译： 非易失性存储器件包括多个存储块，每个存储块被配置为包括多个页面，多个页面缓冲器被配置为对应于多个存储器块并发送回拷数据;控制器，被配置为将拷贝数据发送到页面缓冲器 以及被配置为在回拷程序操作期间从页面中存储已经失败的页面的地址的寄存器。