公开(公告)号：US20090052224A1

公开(公告)日：2009-02-26

申请号：US12228590

申请日：2008-08-14

申请人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

发明人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

IPC分类号： G11C11/22 ,  G11C7/00 ,  G11C7/06

CPC分类号： G11C7/1018 ,  G11C7/08 ,  G11C11/22

摘要： In a ferroelectric random access memory device that can allow a stable burst read operation and a method of driving a ferroelectric random access memory device thereof, the ferroelectric random access memory device comprises first and second memory cell sections, each comprising a plurality of ferroelectric memory cells, and a read circuit that sequentially performs a burst read operation on the first and second memory cell sections such that a read operation of the first memory cell section partially overlaps a read operation of the second memory cell section. When a chip is disabled during the read operation of the first memory cell section, the read circuit writes back data in the second memory cell section in response to the extent to which the read operation of the second memory cell section has been performed.

摘要翻译： 在能够进行稳定的脉冲串读取操作的铁电随机存取存储器件和驱动其铁电随机存取存储器件的方法中，铁电随机存取存储器件包括第一和第二存储单元部分，每个存储单元包括多个铁电存储单元 以及读取电路，其顺序地对第一和第二存储单元部分执行突发读取操作，使得第一存储单元部分的读取操作部分地与第二存储器单元部分的读取操作重叠。 当在第一存储器单元部分的读取操作期间芯片被禁止时，读取电路响应于执行第二存储器单元部分的读取操作的程度将数据写回第二存储器单元部分。

公开(公告)号：US07336549B2

公开(公告)日：2008-02-26

申请号：US11238198

申请日：2005-09-29

申请人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

发明人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

IPC分类号： G11C7/00

CPC分类号： G11C29/789 ,  G11C29/787

摘要： A redundancy circuit and repair method for a semiconductor memory device. The redundancy circuit comprises an address buffer for outputting a first internal address and a second internal address (used only during redundancy programming to carry failed memory addresses) based on an external address; and address storage and comparison units, each one of the address storage and comparison units being selected for programming using the second internal address. The address storage and comparison units comprise ferroelectric storage cells that store the address of a defective (failed) main memory cell and outputs a redundancy decoder enable signal in response to a first internal address matching the stored (second internal) address. Accordingly, the redundancy circuit with ferroelectric storage cells and a repair method allows the performance of a second repair when a defective cell is detected after a first repair or after a packaging process.

摘要翻译： 一种用于半导体存储器件的冗余电路和修复方法。 冗余电路包括用于基于外部地址输出第一内部地址和第二内部地址（仅在冗余编程中使用以携带失败的存储器地址）的地址缓冲器; 以及地址存储和比较单元，使用第二内部地址选择每个地址存储和比较单元进行编程。 地址存储和比较单元包括存储故障（故障）主存储单元的地址的铁电存储单元，并且响应于与存储的（第二内部）地址匹配的第一内部地址而输出冗余解码器使能信号。 因此，具有铁电存储单元的冗余电路和修复方法允许在第一修复或包装处理之后检测到缺陷单元时执行第二次修复。

公开(公告)号：US08467244B2

公开(公告)日：2013-06-18

申请号：US12844621

申请日：2010-07-27

申请人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

发明人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/349

摘要： A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

摘要翻译： 公开了闪存设备和闪存系统。 闪速存储装置包括：第一非易失性存储器，包括多个页数据单元，存储页数据;以及当从外部部分施加读命令时，读出并输出存储的页数据; 以及第二非易失性存储器，其包括分别与所述多个页数据单元相邻的多个备用数据单元，存储备用数据，扫描备用数据并在安装文件系统时临时存储相应的信息，读取并输出所存储的备用 应用读命令时的数据。

公开(公告)号：US20100312954A1

公开(公告)日：2010-12-09

申请号：US12844621

申请日：2010-07-27

申请人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

发明人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

IPC分类号： G06F12/02 ,  H01L23/52 ,  G06F12/00

CPC分类号： G11C16/26 ,  G11C16/349

摘要： A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

摘要翻译： 公开了闪存设备和闪存系统。 闪速存储装置包括：第一非易失性存储器，包括多个页数据单元，存储页数据;以及当从外部部分施加读命令时，读出并输出存储的页数据; 以及第二非易失性存储器，其包括分别与所述多个页数据单元相邻的多个备用数据单元，存储备用数据，扫描备用数据并在安装文件系统时临时存储相应的信息，读取并输出所存储的备用 应用读命令时的数据。

公开(公告)号：US07800931B2

公开(公告)日：2010-09-21

申请号：US12228590

申请日：2008-08-14

申请人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

发明人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

IPC分类号： G11C11/22

CPC分类号： G11C7/1018 ,  G11C7/08 ,  G11C11/22

摘要： In a ferroelectric random access memory device that can allow a stable burst read operation and a method of driving a ferroelectric random access memory device thereof, the ferroelectric random access memory device comprises first and second memory cell sections, each comprising a plurality of ferroelectric memory cells, and a read circuit that sequentially performs a burst read operation on the first and second memory cell sections such that a read operation of the first memory cell section partially overlaps a read operation of the second memory cell section. When a chip is disabled during the read operation of the first memory cell section, the read circuit writes back data in the second memory cell section in response to the extent to which the read operation of the second memory cell section has been performed.

摘要翻译： 在能够进行稳定的脉冲串读取操作的铁电随机存取存储器件和驱动其铁电随机存取存储器件的方法中，铁电随机存取存储器件包括第一和第二存储单元部分，每个存储单元包括多个铁电存储单元 以及读取电路，其顺序地对第一和第二存储单元部分执行突发读取操作，使得第一存储单元部分的读取操作部分地与第二存储器单元部分的读取操作重叠。 当在第一存储器单元部分的读取操作期间芯片被禁止时，读取电路响应于执行第二存储器单元部分的读取操作的程度将数据写回第二存储器单元部分。

公开(公告)号：US07617351B2

公开(公告)日：2009-11-10

申请号：US11567844

申请日：2006-12-07

申请人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

发明人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

IPC分类号： G06F12/00

CPC分类号： G06F12/0638

摘要： A semiconductor memory having two different memory areas in one chip includes a memory cell array including a first variable memory area controlled to be accessible in at least first and second operation modes, and a second variable memory area controlled to be inaccessible in one of the first and second operation modes; and a memory control unit for storing area information discriminating between the first memory area and the second memory area and generating memory control signals for controlling access to the first memory area and the second memory area. One memory can be substituted for a memory combination including ROMs and RAMs in one chip.

摘要翻译： 在一个芯片中具有两个不同存储区域的半导体存储器包括存储单元阵列，该存储单元阵列包括受控于至少第一和第二操作模式可访问的第一可变存储器区域和被控制为在第一和第二操作模式之一不可访问的第二可变存储区域 和第二操作模式; 以及存储器控制单元，用于存储识别第一存储区域和第二存储区域之间的区域信息，并产生用于控制对第一存储区域和第二存储区域的访问的存储器控​​制信号。 一个存储器可以替代包括一个芯片中的ROM和RAM的存储器组合。

公开(公告)号：US20070121367A1

公开(公告)日：2007-05-31

申请号：US11602280

申请日：2006-11-21

申请人： Byung-Gil Jeon ,  Kang-woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

发明人： Byung-Gil Jeon ,  Kang-woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A ferroelectric random access memory (FRAM) device includes a memory cell array including a plurality of FRAM cells connected to a first bit line and a reference cell connected to a second bit line. The device also includes a sense amplifier circuit configured to evaluate an amount of charges induced in a FRAM cell at a first mode and sense data stored in the FRAM cell at a second mode, wherein the sense amplifier circuit comprises a reference voltage generator configured to output an externally applied voltage as a reference voltage at the first mode, and output the reference voltage in response to a voltage applied to the second bit line from the reference cell and a voltage charged to an offset node at the second mode, and an amplifier circuit configured to sense and amplify a difference between a voltage applied to the first bit line from a selected FRAM cell and the reference voltage.

摘要翻译： 铁电随机存取存储器（FRAM）装置包括存储单元阵列，其包括连接到第一位线的多个FRAM单元和连接到第二位线的参考单元。 该装置还包括读出放大器电路，其被配置为评估在第一模式下在FRAM单元中感应的电荷量并且以第二模式感测存储在FRAM单元中的数据，其中读出放大器电路包括参考电压发生器，其被配置为输出 外部施加的电压作为第一模式的参考电压，并且响应于从参考单元施加到第二位线的电压和在第二模式下充电到偏移节点的电压输出参考电压，以及放大器电路 被配置为感测和放大从所选择的FRAM单元施加到第一位线的电压与参考电压之间的差。

公开(公告)号：US20060092750A1

公开(公告)日：2006-05-04

申请号：US11232170

申请日：2005-09-21

申请人： Byung-Gil Jeon ,  Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee

发明人： Byung-Gil Jeon ,  Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C8/14

摘要： A semiconductor memory device having a word line driver circuit configured in stages. A plurality of sub word line driver circuits are connected, in parallel, to each main word line, and provide a sub word line enable signal to a selected sub word line in response to a main word line enable signal provided through a main word line. A plurality of (local) word line driver circuits are connected in parallel, to each sub word line and provide a local word line enable signal to a selected local word line in response to the (main/sub) word line enable signal so as to operate a plurality of memory cells connected to the selected local word line. The transistor count and layout area of a semiconductor memory device decreases and a reduced chip area can be achieved.

摘要翻译： 具有分级配置的字线驱动电路的半导体存储装置。 多个子字线驱动器电路并联连接到每个主字线，并且响应于通过主字线提供的主字线使能信号，向所选择的子字线提供子字线使能信号。 多个（本地）字线驱动电路并联连接到每个子字线，并且响应于（主/副）字线使能信号，向选定的本地字线提供本地字线使能信号，以便 操作连接到所选择的本地字线的多个存储器单元。 半导体存储器件的晶体管数量和布局面积减小，芯片面积减小。

公开(公告)号：US07345945B2

公开(公告)日：2008-03-18

申请号：US11232170

申请日：2005-09-21

申请人： Byung-Gil Jeon ,  Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee

发明人： Byung-Gil Jeon ,  Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C8/14

摘要： A semiconductor memory device having a word line driver circuit configured in stages. A plurality of sub word line driver circuits are connected, in parallel, to each main word line, and provide a sub word line enable signal to a selected sub word line in response to a main word line enable signal provided through a main word line. A plurality of (local) word line driver circuits are connected in parallel, to each sub word line and provide a local word line enable signal to a selected local word line in response to the (main/sub) word line enable signal so as to operate a plurality of memory cells connected to the selected local word line. The transistor count and layout area of a semiconductor memory device decreases and a reduced chip area can be achieved.

摘要翻译： 具有分级配置的字线驱动电路的半导体存储装置。 多个子字线驱动器电路并联连接到每个主字线，并且响应于通过主字线提供的主字线使能信号，向所选择的子字线提供子字线使能信号。 多个（本地）字线驱动电路并联连接到每个子字线，并响应于（主/副）字线使能信号而向所选择的本地字线提供本地字线使能信号，以便 操作连接到所选择的本地字线的多个存储器单元。 半导体存储器件的晶体管数量和布局面积减小，芯片面积减小。

公开(公告)号：US20070035983A1

公开(公告)日：2007-02-15

申请号：US11484280

申请日：2006-07-11

申请人： Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee ,  Byung-Gil Jeon

发明人： Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee ,  Byung-Gil Jeon

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A FeRAM device and a writing section control method therefor, in which the device includes a memory cell constructed of one access transistor and one ferroelectric capacitor; and a writing control circuit for controlling a first writing section to write data of a first logic state in the memory cell and a second writing section to write data of a second logic state different from the first logic state, in response to an external clock signal. Thus a stabilized write operation can be performed and a reliability of data stored in the memory cell can be tested.

摘要翻译： 一种FeRAM器件及其写入部分控制方法，其中该器件包括由一个存取晶体管和一个铁电电容器构成的存储单元; 以及写入控制电路，用于响应于外部时钟信号，控制第一写入部分将存储单元中的第一逻辑状态的数据写入第二写入部分以写入与第一逻辑状态不同的第二逻辑状态的数据 。 因此，可以执行稳定的写入操作，并且可以测试存储在存储单元中的数据的可靠性。