公开(公告)号：US09082366B2

公开(公告)日：2015-07-14

申请号：US13563295

申请日：2012-07-31

申请人： Byung-Hun Han ,  Kyung-Hoon Chung

发明人： Byung-Hun Han ,  Kyung-Hoon Chung

IPC分类号： G09G5/00 ,  G09G3/36 ,  H02M3/07 ,  H02M3/155

CPC分类号： G09G3/3696 ,  G09G2330/021 ,  G09G2330/026 ,  G09G2330/028 ,  H02M3/07 ,  H02M3/155

摘要： A power converting circuit of a display driver includes a positive voltage generator and a negative voltage generator. The positive voltage generator includes a first capacitive DC-DC converter and a first inductive DC-DC converter, and generates a positive source voltage by selectively using one of the first capacitive DC-DC converter, the first inductive DC-DC converter, or a first external power supply voltage. The negative voltage generator includes a second capacitive DC-DC converter and a second inductive DC-DC converter, and generates a negative source voltage by selectively using one of the second capacitive DC-DC converter, the second inductive DC-DC converter, or a second external power supply voltage.

摘要翻译： 显示驱动器的电力转换电路包括正电压发生器和负电压发生器。 正电压发生器包括第一电容DC-DC转换器和第一电感DC-DC转换器，并且通过选择性地使用第一电容DC-DC转换器，第一电感DC-DC转换器或 第一个外部电源电压。 负电压发生器包括第二电容DC-DC转换器和第二电感DC-DC转换器，并且通过选择性地使用第二电容DC-DC转换器，第二电感DC-DC转换器或 第二个外部电源电压。

公开(公告)号：US20050104647A1

公开(公告)日：2005-05-19

申请号：US10987430

申请日：2004-11-12

申请人： Chul Choi ,  Jae-Goo Lee ,  Byung-Hun Han

发明人： Chul Choi ,  Jae-Goo Lee ,  Byung-Hun Han

IPC分类号： G09G3/36 ,  G02F1/133 ,  G06F1/04 ,  G09G3/20 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/0185 ,  H04N5/66

CPC分类号： G06F1/04

摘要： Provided are a level shifter circuit and a corresponding method for controlling voltage levels of a clock signal and an inverted clock signal for driving gate lines of a ASG thin film transistor liquid crystal display panel, where the level shifter circuit includes first and second level shifters, the first level shifter controls the voltage level of the clock signal to swing between a negative external voltage level and a positive external voltage level in response to a clock activating signal, and increases the voltage level of the clock signal from the negative external voltage level to a power supply voltage level or decreases it from the positive external voltage level to a ground voltage level while a pre-charge clock activating signal is activated, the second level shifter controls the voltage level of the inverted clock signal to swing between the negative external voltage level and the positive external voltage level in response to an inverted clock activating signal, and increases the voltage level of the inverted clock signal from the negative external voltage level to the power supply voltage level or decreases it from the positive external voltage level to the ground voltage level while an inverted pre-charge clock activating signal is activated, and the level shifter circuit increases or decreases the voltage levels of the clock signal and inverted clock signal using a battery voltage or a ground voltage, thereby reducing current consumption caused by the increase or decrease in the voltage level.

摘要翻译： 提供了一种用于控制用于驱动ASG薄膜晶体管液晶显示面板的栅极线的时钟信号和反相时钟信号的电压电平的电平移位器电路和相应方法，其中电平移位器电路包括第一和第二电平移位器， 第一电平移位器响应于时钟激活信号控制时钟信号的电压电平在负的外部电压电平和正的外部电压电平之间摆动，并且将时钟信号的电压电平从负的外部电压电平提高到 电源电压电平或者从正的外部电压电平降低到接地电压电平，同时预充电时钟激活信号被激活，第二电平移位器控制反相时钟信号的电压电平在负外部电压之间摆动 电平和正的外部电压电平响应于反相时钟激活信号，并且包括 将反相时钟信号的电压电平从负外部电压电平降低到电源电压电平，或将其从正外部电压电平降低到接地电压电平，同时反相的预充电时钟激活信号被激活，并且电平 移位器电路使用电池电压或接地电压来增加或减少时钟信号和反相时钟信号的电压电平，由此降低由电压电平的增加或减少引起的电流消耗。

公开(公告)号：US20070046599A1

公开(公告)日：2007-03-01

申请号：US11324036

申请日：2005-12-30

申请人： Kyung-Myun Kim ,  Kyeong-Tae Moon ,  Byung-Hun Han ,  Sang-Hun Kim

发明人： Kyung-Myun Kim ,  Kyeong-Tae Moon ,  Byung-Hun Han ,  Sang-Hun Kim

IPC分类号： G09G3/36

CPC分类号： G09G3/3696 ,  G09G3/3611 ,  G09G3/3688 ,  G09G2320/0233 ,  H05K3/361

摘要： A display device includes a display panel having a plurality of scan lines and a plurality of data lines, and a plurality of display panel driving apparatuses. Each of the display panel driving apparatuses includes a data line driving circuit, and a plurality of pads via which corresponding gray-scale voltages are respectively output. The data line driving circuit drives corresponding data lines of the plurality of the data lines. Each of the plurality of the pads outputs a corresponding gray-scale voltage of a plurality of gray-scale voltages, wherein the pads of the display panel driving apparatuses are connected in a cascade. The pads of the display panel driving apparatuses may be connected via a flexible printed circuit.

摘要翻译： 显示装置包括具有多条扫描线和多条数据线的显示面板和多个显示面板驱动装置。 每个显示面板驱动装置包括数据线驱动电路和分别输出对应的灰度电压的多个焊盘。 数据线驱动电路驱动多条数据线的对应的数据线。 多个焊盘中的每一个输出多个灰度电压的对应的灰度电压，其中显示面板驱动装置的焊盘级联连接。 显示面板驱动装置的焊盘可以经由柔性印刷电路连接。

公开(公告)号：US07466312B2

公开(公告)日：2008-12-16

申请号：US10987430

申请日：2004-11-12

申请人： Chul Choi ,  Jae-Goo Lee ,  Byung-Hun Han

发明人： Chul Choi ,  Jae-Goo Lee ,  Byung-Hun Han

IPC分类号： G09G3/36 ,  G09G3/38

CPC分类号： G06F1/04

摘要： Provided are a level shifter circuit and a corresponding method for controlling voltage levels of a clock signal and an inverted clock signal for driving gate lines of a ASG thin film transistor liquid crystal display panel, where the level shifter circuit includes first and second level shifters, the first level shifter controls the voltage level of the clock signal to swing between a negative external voltage level and a positive external voltage level in response to a clock activating signal, and increases the voltage level of the clock signal from the negative external voltage level to a power supply voltage level or decreases it from the positive external voltage level to a ground voltage level while a pre-charge clock activating signal is activated, the second level shifter controls the voltage level of the inverted clock signal to swing between the negative external voltage level and the positive external voltage level in response to an inverted clock activating signal, and increases the voltage level of the inverted clock signal from the negative external voltage level to the power supply voltage level or decreases it from the positive external voltage level to the ground voltage level while an inverted pre-charge clock activating signal is activated, and the level shifter circuit increases or decreases the voltage levels of the clock signal and inverted clock signal using a battery voltage or a ground voltage, thereby reducing current consumption caused by the increase or decrease in the voltage level.

摘要翻译： 提供了一种用于控制用于驱动ASG薄膜晶体管液晶显示面板的栅极线的时钟信号和反相时钟信号的电压电平的电平移位器电路和相应方法，其中电平移位器电路包括第一和第二电平移位器， 第一电平移位器响应于时钟激活信号控制时钟信号的电压电平在负的外部电压电平和正的外部电压电平之间摆动，并且将时钟信号的电压电平从负的外部电压电平提高到 电源电压电平或者从正的外部电压电平降低到接地电压电平，同时预充电时钟激活信号被激活，第二电平移位器控制反相时钟信号的电压电平在负外部电压之间摆动 电平和正的外部电压电平响应于反相时钟激活信号，并且包括 将反相时钟信号的电压电平从负外部电压电平降低到电源电压电平，或将其从正外部电压电平降低到接地电压电平，同时反相的预充电时钟激活信号被激活，并且电平 移位器电路使用电池电压或接地电压来增加或减少时钟信号和反相时钟信号的电压电平，由此降低由电压电平的增加或减少引起的电流消耗。

公开(公告)号：US6100769A

公开(公告)日：2000-08-08

申请号：US274401

申请日：1999-03-23

申请人： Byung-Kwon An ,  Byung-Hun Han

发明人： Byung-Kwon An ,  Byung-Hun Han

IPC分类号： H03K3/0231 ,  H03K3/03 ,  H03B5/02

CPC分类号： H03K3/03 ,  H03K3/0231 ,  H03K3/0322

摘要： A differential delay circuit type ring oscillator allows for an increase in operation enabling frequency and dynamic range. At each stage of the ring, delay circuit output signals arc linearly varied above and below the circuit switching level. The ring oscillator includes a plurality of differential delay circuits coupled in series in a ring configuration, a differential amplifier, and a comparator. Each of the differential delay circuits receives first and second differential input signals, and delays the received signals by a predetermined time in response to a predetermined control signal to generate first and second differential output signals. The differential amplifier receives the first and the second differential output signals of one of the differential delay circuits and amplifies the received signals to generate first and second differential amplified signals. The comparator receives first and the second differential amplified signals, and compares them to generate an oscillating signal in accordance with the comparison results.

摘要翻译： 差分延迟电路型环形振荡器允许增加工作频率和动态范围。 在环的每个阶段，延迟电路输出信号在电路开关电平之上和之下呈线性变化。 环形振荡器包括以环形配置串联耦合的多个差分延迟电路，差分放大器和比较器。 每个差分延迟电路接收第一和第二差分输入信号，并且响应于预定控制信号将接收信号延迟预定时间以产生第一和第二差分输出信号。 差分放大器接收差分延迟电路之一的第一和第二差分输出信号，并放大接收信号以产生第一和第二差分放大信号。 比较器接收第一和第二差分放大信号，并根据比较结果进行比较以产生振荡信号。