公开(公告)号：US09160582B1

公开(公告)日：2015-10-13

申请号：US14230121

申请日：2014-03-31

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Scott Huss ,  Chris Moscone ,  James Vandersand, Jr.

IPC: H04B1/10 ,  H04L25/03

CPC classification number: H04L25/03885 ,  H03L7/0807 ,  H03L7/089 ,  H04L7/033 ,  H04L25/03146

Abstract: A system and method are provided for phase recovery of a signal received by a receiver having digital equalization. A sample acquisition unit periodically acquires a plurality of I and Q samples of the received signal. The sample acquisition unit includes a delay portion to enable selective mutual comparisons between a current I sample ID0, a first preceding I samples ID1, and a second preceding I sample ID2. A transition detection unit generates at least one transition detect signal responsive to the ID1, ID0, and Q samples. The transition detect signal indicates a logic state transition in the received signal between the ID1 and ID0 samples. A transition filtering unit generates an equalization detect signal indicative of excessive equalizing correction of the received signal at the ID0 sample, and selectively passes in response the transition detect signal as a timing output signal.

Abstract translation: 提供了一种用于相位恢复由具有数字均衡的接收机接收的信号的系统和方法。 采样单元周期性地获取接收信号的多个I和Q采样。 样本获取单元包括延迟部分，以使得能够在当前I个样本ID0，前一个I个样本ID1和第二个先前的样本ID2之间进行选择性的相互比较。 转移检测单元响应于ID1，ID0和Q样本产生至少一个转换检测信号。 转移检测信号表示ID1和ID0采样之间的接收信号中的逻辑状态转换。 转换滤波单元产生指示在ID0采样时对接收信号进行过度均衡校正的均衡检测信号，并且响应地选择性地通过转换检测信号作为定时输出信号。

公开(公告)号：US09071256B1

公开(公告)日：2015-06-30

申请号：US14311648

申请日：2014-06-23

Applicant: Cadence Design Systems, Inc.

Inventor： Loren Blair Reiss ,  Chris Moscone ,  Benjamin Louis Heilmann ,  Randall Smith

IPC: H03M9/00

CPC classification number: H03M9/00

Abstract: The present disclosure relates to a method for use with a serializer/deserializer comprising. The method may include grouping one or more lane modules associated with an integrated circuit (IC) together to form a link, wherein each of the one or more lane modules includes a reset state machine and a high speed reset generator. The method may also include providing a common module having a common reset release state machine and a reset release synchronizer and pulse generator, the common module and one or more lane modules being configured to communicate therebetween. The method may further include resetting each link independently using the one or more lane modules.

Abstract translation: 本公开涉及一种与串行器/解串器一起使用的方法，包括： 该方法可以包括将与集成电路（IC）相关联的一个或多个通道模块组合在一起以形成链路，其中一个或多个通道模块中的每一个包括复位状态机和高速复位发生器。 该方法还可以包括提供具有公共复位释放状态机和复位释放同步器和脉冲发生器的公共模块，所述公共模块和一个或多个通道模块被配置为在它们之间通信。 该方法还可以包括使用一个或多个车道模块独立地重置每个链路。