公开(公告)号：US20110216279A1

公开(公告)日：2011-09-08

申请号：US13108782

申请日：2011-05-16

申请人： CHANG-HUN LEE ,  Eun-Hee Han ,  Hak-Sun Chang

发明人： CHANG-HUN LEE ,  Eun-Hee Han ,  Hak-Sun Chang

IPC分类号： G02F1/1343

CPC分类号： G02F1/134363 ,  G02F1/136213 ,  G02F2201/128 ,  G02F2201/40

摘要： Disclosed is a liquid crystal display capable of high quality image and bright display. Gate signal lines are curved at near switching elements of the liquid crystal display. A pixel area is defined by the gate signal lines and their intersecting data signal lines. Pixel electrodes and common electrodes are disposed along a longitudinal direction of a pixel. A pixel signal and a common signal line is connected to the pixel electrode and the common electrode respectively. A storage capacitor may be formed in the middle of a longitudinal direction of the pixel, or where generally a texture may arise during display. One half of the pixel may be symmetrical with the other half with respect to the storage capacitor. A common signal line may be parallel with the data signal line and be disposed nearer to the data signal line than a pixel signal line. The pixel may be disposed symmetrically with respect to the data signal line therebetween. The pixel shape may also be repeated in the direction of the gate signal line.

摘要翻译： 公开了一种具有高质量图像和明亮显示的液晶显示器。 栅极信号线在液晶显示器的开关元件附近弯曲。 像素区域由栅极信号线及其相交的数据信号线限定。 像素电极和公共电极沿着像素的纵向方向设置。 像素信号和公共信号线分别连接到像素电极和公共电极。 存储电容器可以形成在像素的纵向方向的中间，或者在显示期间通常可能出现纹理。 像素的一半可以与存储电容器的另一半对称。 公共信号线可以与数据信号线并联，并且被设置为比像素信号线更靠近数据信号线。 像素可以相对于它们之间的数据信号线对称地设置。 像素形状也可以在栅极信号线的方向上重复。

公开(公告)号：US20080315289A1

公开(公告)日：2008-12-25

申请号：US12199307

申请日：2008-08-27

申请人： JAE HWANG KIM ,  SEUNG-BEOM YOON ,  KWANG-WOOK KOH ,  CHANG-HUN LEE ,  SUNG-HO KIM ,  SUNG-CHUL PARK ,  JU-RI KIM

发明人： JAE HWANG KIM ,  SEUNG-BEOM YOON ,  KWANG-WOOK KOH ,  CHANG-HUN LEE ,  SUNG-HO KIM ,  SUNG-CHUL PARK ,  JU-RI KIM

IPC分类号： H01L29/00

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate.

摘要翻译： EEPROM器件包括设置在半导体衬底的预定区域以限定有源区的器件隔离层，与器件隔离层交叉的一对控制栅极和有源区，插入控制栅极之间的一对选择栅极， 器件隔离层和有源区以及顺序地堆叠在控制栅极和有源区之间的浮置栅极和隔间栅极电介质图案。EEPROM器件还包括插入浮置栅极和有源区域之间的存储晶体管的栅极绝缘层，以及 隧道绝缘层比存储晶体管的栅极绝缘层薄，并且选择晶体管的栅极绝缘层插入在选择栅极和有源区之间。 隧道绝缘层在与浮动栅极相邻的一侧对准。