公开(公告)号：US11862268B2

公开(公告)日：2024-01-02

申请号：US17595456

申请日：2020-10-15

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Chuanqi Shi ,  Heng-Chia Chang ,  Li Ding ,  Jie Liu ,  Jun He ,  Zhan Ying

IPC: G11C29/10 ,  G11C29/36 ,  G11C29/56 ,  G11C29/40

CPC classification number: G11C29/10 ,  G11C29/36 ,  G11C29/56 ,  G11C29/56004 ,  G11C2029/4002

Abstract: Embodiments of the present disclosure provide a test method and apparatus for a control chip, an electronic device, relating to the field of semiconductor device test technology. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, a memory chip can be used for storing test vectors for a control chip, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.

公开(公告)号：US12045150B2

公开(公告)日：2024-07-23

申请号：US17595454

申请日：2020-10-15

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Heng-Chia Chang ,  Chuanqi Shi ,  Li Ding

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/22 ,  G06F11/27

CPC classification number: G06F11/27 ,  G06F11/0793 ,  G06F11/2268

Abstract: Embodiments of the present disclosure provide a memory test method and a device thereof, an electronic device, and a computer-readable storage medium, which relate to the field of semiconductor device testing technologies. The method is executed by a built-in self-test circuit and includes: acquiring defect information of a first memory by testing the first memory; acquiring repair information of the first memory based on the defect information of the first memory; and storing the repair information of the first memory in a second memory.

公开(公告)号：US11867758B2

公开(公告)日：2024-01-09

申请号：US17595452

申请日：2020-10-15

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Chuanqi Shi ,  Heng-Chia Chang ,  Li Ding ,  Jie Liu ,  Jun He ,  Zhan Ying

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3193 ,  G01R31/319 ,  G11C29/56 ,  G01R31/28 ,  G01R31/3187 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/2834 ,  G01R31/2856 ,  G01R31/3187 ,  G01R31/3193 ,  G01R31/31713 ,  G01R31/31724 ,  G01R31/31917 ,  G01R31/31932 ,  G01R31/318566 ,  G11C29/56 ,  G11C2029/5602

Abstract: Embodiments of the present disclosure provide a test method and apparatus for a control chip, and an electronic device, which relate to the field of semiconductor device test technologies. The control chip includes a built-in self-test BIST circuit. The method is performed by the BIST circuit. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.

公开(公告)号：US11854642B2

公开(公告)日：2023-12-26

申请号：US17310414

申请日：2020-10-15

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Heng-Chia Chang ,  Li Ding ,  Chuanqi Shi

IPC: G11C29/46 ,  G11C29/44 ,  G11C29/56

CPC classification number: G11C29/46 ,  G11C29/4401 ,  G11C29/56004

Abstract: A memory test method includes: testing a first memory to acquire defect information of the first memory; acquiring repair information of the first memory according to the defect information of the first memory; and storing the repair information of the first memory in a second memory. In the technical solutions provided in the embodiments of the present disclosure, other memories may be used to store the repair information of the currently tested memory, so that the storage space can be increased and the test efficiency can be improved.