公开(公告)号：US12089400B2

公开(公告)日：2024-09-10

申请号：US17452272

申请日：2021-10-26

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Minki Hong

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02 ,  H10B12/00

CPC classification number: H10B12/482 ,  H01L28/60 ,  H01L29/66666 ,  H01L29/7827 ,  H10B12/038

Abstract: The present disclosure provides a method for forming a semiconductor structure and a semiconductor structure. The method for forming a semiconductor structure includes: providing a substrate, and forming discrete bit line structures on the substrate; forming a first sacrificial layer on the surface of the substrate on the bottoms of gaps of the bit line structures; forming a second sacrificial layer filling the gaps of the discrete bit line structures; patterning the second sacrificial layer and the first sacrificial layer to form openings, the formed openings and the remaining of the second sacrificial layer being arranged alternately in an extension direction of the bit line structures; forming a dielectric layer filling the openings; and, removing the remaining of the first sacrificial layer and the remaining of the second sacrificial layer to form capacitor contact holes, the formed capacitor contact holes and the dielectric layer being arranged alternately.

公开(公告)号：US20220293609A1

公开(公告)日：2022-09-15

申请号：US17452272

申请日：2021-10-26

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Minki Hong

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02

Abstract: The present disclosure provides a method for forming a semiconductor structure and a semiconductor structure. The method for forming a semiconductor structure includes: providing a substrate, and forming discrete bit line structures on the substrate; forming a first sacrificial layer on the surface of the substrate on the bottoms of gaps of the bit line structures; forming a second sacrificial layer filling the gaps of the discrete bit line structures; patterning the second sacrificial layer and the first sacrificial layer to form openings, the formed openings and the remaining of the second sacrificial layer being arranged alternately in an extension direction of the bit line structures; forming a dielectric layer filling the openings; and, removing the remaining of the first sacrificial layer and the remaining of the second sacrificial layer to form capacitor contact holes, the formed capacitor contact holes and the dielectric layer being arranged alternately.