公开(公告)号：US12033920B2

公开(公告)日：2024-07-09

申请号：US17511844

申请日：2021-10-27

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Pingheng Wu

IPC: H01L23/48 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/76877 ,  H01L21/76898 ,  H01L25/0657

Abstract: The present application relates to the field of semiconductor technologies, and discloses a semiconductor structure and a formation method thereof. The method includes: providing a semiconductor substrate, the semiconductor substrate including a TSV; forming a dielectric layer on a surface of the semiconductor substrate, the dielectric layer being provided with an embedded metal landing pad; and etching the dielectric layer to form a communication hole for communicating the TSV with the metal landing pad.

公开(公告)号：US11894226B2

公开(公告)日：2024-02-06

申请号：US17432478

申请日：2020-06-19

Applicant: ChangXin Memory Technologies, Inc.

Inventor： Pingheng Wu

IPC: H01L21/02 ,  H01L21/027

CPC classification number: H01L21/02118 ,  H01L21/02002 ,  H01L21/0274 ,  H01L21/02345

Abstract: A fabrication method of a semiconductor device comprises the steps of: providing a substrate, which is divided into several chip areas; forming a protective layer on the substrate, the protective layer covers the scribe lines and the chip areas; exposing and developing the protective layer to form a plurality of grooves in the protective layer over the chip areas, and the depth of the grooves is smaller than the initial thickness of the protective layer.

公开(公告)号：US12027418B2

公开(公告)日：2024-07-02

申请号：US17435967

申请日：2020-09-17

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Pingheng Wu

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/535

CPC classification number: H01L21/76844 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76895 ,  H01L23/5283 ,  H01L23/535 ,  H01L21/76838 ,  H01L21/76885

Abstract: The present disclosure relates to a semiconductor device and a preparation method thereof. The method for preparing a semiconductor device comprises: providing a first dielectric layer; forming a first window in the first dielectric layer; forming a first connection structure in the first window; forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a second window from which at least the first connection structure is exposed; forming a first barrier layer on the sidewall and bottom of the second window, the first barrier layer comprising an opening from which part of the first connection structure is exposed; and forming a second connection structure in the second window.

公开(公告)号：US11769674B2

公开(公告)日：2023-09-26

申请号：US17236933

申请日：2021-04-21

Applicant: Changxin Memory Technologies, Inc.

Inventor： Pingheng Wu

IPC: H01L21/48 ,  H01L21/768 ,  H01L23/522 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L21/486 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/5226 ,  H01L24/11 ,  H01L24/14 ,  H01L25/0657

Abstract: A semiconductor interconnect structure and a fabricating method thereof are disclosed. The method comprises: providing a stacked structure comprising bonded multiple layers of wafer or die, each bonded layer comprises a substrate and a wiring layer, and the wiring layer comprises metal wires; vertically forming, in the stacked structure, a first blind hole having a first diameter and a first length and penetrating each bonded layer between adjacent metal wires, the first diameter is less than a space between the adjacent metal wires, and the first length is less than a height of the stacked structure; forming a second blind hole having a second diameter and the first length coaxially with the first blind hole, a sidewall of the second blind hole exposes the metal wires, and the second diameter is larger than the space between the adjacent metal wires; and filling a conductive material in the second blind hole.

公开(公告)号：US20220139700A1

公开(公告)日：2022-05-05

申请号：US17432478

申请日：2020-06-19

Applicant: ChangXin Memory Technologies, Inc.

Inventor： Pingheng Wu

IPC: H01L21/02 ,  H01L21/027

Abstract: A fabrication method of a semiconductor device comprises the steps of: providing a substrate, which is divided into several chip areas; forming a protective layer on the substrate, the protective layer covers the scribe lines and the chip areas; exposing and developing the protective layer to form a plurality of grooves in the protective layer over the chip areas, and the depth of the grooves is smaller than the initial thickness of the protective layer.