专利检索 ap:("CHANKYUNG KIM" OR "UKSONG KANG" OR "Nam Sung KIM") AND inv:"Nam Sung KIM" 第 1 页

1.

发明申请
MEMORY PACKAGE, MEMORY MODULE INCLUDING THE SAME, AND OPERATION METHOD OF MEMORY PACKAGE 审中-公开

公开(公告)号：US20180108383A1

公开(公告)日：2018-04-19

申请号：US15820473

申请日：2017-11-22

申请人： CHANKYUNG KIM , UKSONG KANG , Nam Sung KIM

发明人： CHANKYUNG KIM , UKSONG KANG , Nam Sung KIM

IPC分类号： G11C5/02 , G11C5/06 , G06F12/06 , G11C11/406

CPC分类号： G11C5/02 , G06F12/0638 , G06F13/1636 , G06F2212/205 , G11C5/025 , G11C5/06 , G11C8/12 , G11C11/40611 , G11C14/0009

摘要： Disclosed is a memory package. The memory package includes a nonvolatile memory chip, a volatile memory chip of which an access speed is faster than an access speed of the nonvolatile memory chip, and a logic chip for performing a refresh operation about the volatile memory chip in response to a refresh command from an external device, and migrating at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip when the refresh operation is performed.

2.

发明申请
MEMORY MODULE, MEMORY DEVICE, AND PROCESSING DEVICE HAVING A PROCESSOR MODE, AND MEMORY SYSTEM 审中-公开

公开(公告)号：US20180107406A1

公开(公告)日：2018-04-19

申请号：US15603255

申请日：2017-05-23

申请人： SEONG-IL O , Nam Sung KIM , Young-Hoon SON , Chan-Kyung KIM , Ho-Young SONG , Jung Ho AHN , Sang-Joon HWANG

发明人： SEONG-IL O , Nam Sung KIM , Young-Hoon SON , Chan-Kyung KIM , Ho-Young SONG , Jung Ho AHN , Sang-Joon HWANG

IPC分类号： G06F3/06 , G06F13/16

CPC分类号： G06F3/0611 , G06F3/0656 , G06F3/0659 , G06F3/0683 , G06F13/1673

摘要： A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.