公开(公告)号：US20180108383A1

公开(公告)日：2018-04-19

申请号：US15820473

申请日：2017-11-22

申请人： CHANKYUNG KIM ,  UKSONG KANG ,  Nam Sung KIM

发明人： CHANKYUNG KIM ,  UKSONG KANG ,  Nam Sung KIM

IPC分类号： G11C5/02 ,  G11C5/06 ,  G06F12/06 ,  G11C11/406

CPC分类号： G11C5/02 ,  G06F12/0638 ,  G06F13/1636 ,  G06F2212/205 ,  G11C5/025 ,  G11C5/06 ,  G11C8/12 ,  G11C11/40611 ,  G11C14/0009

摘要： Disclosed is a memory package. The memory package includes a nonvolatile memory chip, a volatile memory chip of which an access speed is faster than an access speed of the nonvolatile memory chip, and a logic chip for performing a refresh operation about the volatile memory chip in response to a refresh command from an external device, and migrating at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip when the refresh operation is performed.

公开(公告)号：US20050018514A1

公开(公告)日：2005-01-27

申请号：US10881022

申请日：2004-06-30

申请人： Roland Knaack ,  David Gibson ,  Mario Montana ,  Mario Au ,  Stewart Speed ,  Srinivas Bamdhamravuri ,  Uksong Kang

发明人： Roland Knaack ,  David Gibson ,  Mario Montana ,  Mario Au ,  Stewart Speed ,  Srinivas Bamdhamravuri ,  Uksong Kang

IPC分类号： G06F5/06 ,  G11C7/00

CPC分类号： G06F5/06

摘要： An integrated circuit chip includes a plurality of independent FIFO memory devices that are each configured to support all four combinations of DDR and SDR write modes and DDR and SDR read modes and collectively configured to support all four multiplexer, demultiplexer, broadcast and multi-Q operating modes.

摘要翻译： 集成电路芯片包括多个独立的FIFO存储器件，其各自被配置为支持DDR和SDR写入模式以及DDR和SDR读取模式的所有四种组合，并且共同配置为支持所有四个多路复用器，解复用器，广播和多Q操作 模式。

公开(公告)号：US07082071B2

公开(公告)日：2006-07-25

申请号：US10881022

申请日：2004-06-30

申请人： Roland T. Knaack ,  David Stuart Gibson ,  Mario Montana ,  Mario Au ,  Stewart Speed ,  Srinivas Satish Babu Bamdhamravuri ,  Uksong Kang

发明人： Roland T. Knaack ,  David Stuart Gibson ,  Mario Montana ,  Mario Au ,  Stewart Speed ,  Srinivas Satish Babu Bamdhamravuri ,  Uksong Kang

IPC分类号： G11C7/00

CPC分类号： G06F5/06

摘要： An integrated circuit chip includes a plurality of independent FIFO memory devices that are each configured to support all four combinations of DDR and SDR write modes and DDR and SDR read modes and collectively configured to support all four multiplexer, demultiplexer, broadcast and multi-Q operating modes.

摘要翻译： 集成电路芯片包括多个独立的FIFO存储器件，其各自被配置为支持DDR和SDR写入模式以及DDR和SDR读取模式的所有四种组合，并且共同配置为支持所有四个多路复用器，解复用器，广播和多Q操作 模式。

公开(公告)号：US20160055052A1

公开(公告)日：2016-02-25

申请号：US14678977

申请日：2015-04-04

申请人： Chaohong HU ,  Hongzhong ZHENG ,  Uksong KANG ,  Zhan PING

发明人： Chaohong HU ,  Hongzhong ZHENG ,  Uksong KANG ,  Zhan PING

IPC分类号： G06F11/10 ,  G06F3/06

CPC分类号： G06F11/10 ,  G06F11/1008 ,  G06F11/1076

摘要： An embodiment includes a memory module, comprising: a module error interface; and a plurality of memory devices, each memory device coupled to the module error interface, including a data interface and an device error interface, and configured to communicate error information through the device error interface and the module error interface.

摘要翻译： 实施例包括存储器模块，包括：模块错误接口; 以及多个存储器件，每个存储器件耦合到所述模块错误接口，包括数据接口和设备错误接口，并且被配置为通过所述设备错误接口和所述模块错误接口传送错误信息。

公开(公告)号：US20170220293A1

公开(公告)日：2017-08-03

申请号：US15012845

申请日：2016-02-01

申请人： Chankyung KIM ,  Uksong Kang ,  Nam Sung Kim

发明人： Chankyung KIM ,  Uksong Kang ,  Nam Sung Kim

IPC分类号： G06F3/06 ,  G11C5/02 ,  G11C5/06 ,  G06F12/02 ,  G11C11/406

CPC分类号： G11C5/02 ,  G06F12/0638 ,  G06F2212/205 ,  G11C5/025 ,  G11C5/06 ,  G11C8/12 ,  G11C11/40611 ,  G11C14/0009

摘要： Disclosed is a memory package. The memory package includes a nonvolatile memory chip, a volatile memory chip of which an access speed is faster than an access speed of the nonvolatile memory chip, and a logic chip for performing a refresh operation about the volatile memory chip in response to a refresh command from an external device, and migrating at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip when the refresh operation is performed.

公开(公告)号：US20160055059A1

公开(公告)日：2016-02-25

申请号：US14678968

申请日：2015-04-04

申请人： Chaohong HU ,  Liang YIN ,  Hongzhong ZHENG ,  Uksong KANG

发明人： Chaohong HU ,  Liang YIN ,  Hongzhong ZHENG ,  Uksong KANG

IPC分类号： G06F11/10

CPC分类号： G06F11/10 ,  G06F11/1008 ,  G06F11/1076

摘要： An embodiment includes a memory device, comprising: a memory configured to store data; a data interface; an error interface; and a controller coupled to the data interface, the error interface, and the memory. The controller is configured to transmit data stored in the memory through the data interface; and the controller is configured to transmit error information generated in response to correcting an error in data read from memory through the error interface.

摘要翻译： 实施例包括存储器设备，包括：存储器，被配置为存储数据; 数据接口; 错误界面 以及耦合到数据接口，错误接口和存储器的控制器。 控制器被配置为通过数据接口传送存储在存储器中的数据; 并且所述控制器被配置为发送响应于通过所述错误接口校正从存储器读取的数据中的错误而生成的错误信息。