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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08396682B2

    公开(公告)日：2013-03-12

    申请号：US12900547

    申请日：2010-10-08

    申请人： Chi-Sung Oh ,  Dong-Hyuk Lee ,  Ho-Cheol Lee ,  Jang-Woo Ryu ,  Jung-Bae Lee

    发明人： Chi-Sung Oh ,  Dong-Hyuk Lee ,  Ho-Cheol Lee ,  Jang-Woo Ryu ,  Jung-Bae Lee

    IPC分类号： G01R27/28 ,  G06F19/00

    CPC分类号： G01R31/2884 ,  G01R31/31726

    摘要： A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip.

    摘要翻译： 提供半导体器件。 半导体器件将通过测试焊盘安装有凸块的凸块焊盘施加的数据施加到测试装置，使得可以提高测试的可靠性。 通过允许通过凸块焊盘的数据输出被选择性地施加到测试焊盘，测试焊盘的量显着减少。 从测试焊盘施加的数据和信号彼此同步，并在测试操作期间应用于凸块焊盘，从而可以提高测试的可靠性，而无需额外的测试芯片。

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20110093235A1

    公开(公告)日：2011-04-21

    申请号：US12900547

    申请日：2010-10-08

    申请人： CHI-SUNG OH ,  Dong-Hyuk Lee ,  Ho-Cheol Lee ,  Jang-Woo Ryu ,  Jung-Bae Lee

    发明人： CHI-SUNG OH ,  Dong-Hyuk Lee ,  Ho-Cheol Lee ,  Jang-Woo Ryu ,  Jung-Bae Lee

    IPC分类号： G01R31/14 ,  H03L7/00

    CPC分类号： G01R31/2884 ,  G01R31/31726

    摘要： A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip.

    摘要翻译： 提供半导体器件。 半导体器件将通过测试焊盘安装有凸块的凸块焊盘施加的数据施加到测试装置，使得可以提高测试的可靠性。 通过允许通过凸块焊盘的数据输出被选择性地施加到测试焊盘，测试焊盘的量显着减少。 从测试焊盘施加的数据和信号彼此同步，并在测试操作期间应用于凸块焊盘，从而可以提高测试的可靠性，而无需额外的测试芯片。

    SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20100177576A1

    公开(公告)日：2010-07-15

    申请号：US12686561

    申请日：2010-01-13

    申请人： Chi-Sung Oh ,  Jung-Bae Lee ,  Dong-Hyuk Lee

    发明人： Chi-Sung Oh ,  Jung-Bae Lee ,  Dong-Hyuk Lee

    IPC分类号： G11C7/08

    CPC分类号： G11C7/065 ,  G11C5/025 ,  G11C7/08 ,  G11C11/4091

    摘要： A semiconductor memory device includes a sense amplifier, a sense amplifier driving signal driver, and a controller. The sense amplifier is configured to sense and amplify a signal of a bit line and a signal of a complementary bit line in response to a sense amplifier driving signal. The sense amplifier driving signal driver includes a first driving signal driver configured to drive via a transmission line the sense amplifier driving signal in response to a first sense amplifier control signal, and a second driving signal driver configured to drive via the transmission line the sense amplifier driving signal in response to a second sense amplifier control signal. The controller activates the first sense amplifier control signal in response to an active command, and toggles the second sense amplifier control signal while the first sense amplifier control signal is activated.

    摘要翻译： 半导体存储器件包括读出放大器，读出放大器驱动信号驱动器和控制器。 读出放大器被配置为响应于读出放大器驱动信号来检测和放大位线的信号和互补位线的信号。 读出放大器驱动信号驱动器包括：第一驱动信号驱动器，被配置为响应于第一读出放大器控制信号经由传输线驱动读出放大器驱动信号;以及第二驱动信号驱动器，被配置为通过传输线驱动读出放大器 响应于第二读出放大器控制信号的驱动信号。 控制器响应于有效命令激活第一读出放大器控制信号，并且在第一读出放大器控制信号被激活时切换第二读出放大器控制信号。

    Semiconductor memory device in which a method of controlling a BIT line sense amplifier is improved
    4.
    发明授权
    Semiconductor memory device in which a method of controlling a BIT line sense amplifier is improved 有权
    提高了控制BIT线读出放大器的方法的半导体存储器件

    公开(公告)号：US08120980B2

    公开(公告)日：2012-02-21

    申请号：US12686561

    申请日：2010-01-13

    申请人： Chi-Sung Oh ,  Jung-Bae Lee ,  Dong-Hyuk Lee

    发明人： Chi-Sung Oh ,  Jung-Bae Lee ,  Dong-Hyuk Lee

    IPC分类号： G11C7/02

    CPC分类号： G11C7/065 ,  G11C5/025 ,  G11C7/08 ,  G11C11/4091

    摘要： A semiconductor memory device includes a sense amplifier, a sense amplifier driving signal driver, and a controller. The sense amplifier is configured to sense and amplify a signal of a bit line and a signal of a complementary bit line in response to a sense amplifier driving signal. The sense amplifier driving signal driver includes a first driving signal driver configured to drive via a transmission line the sense amplifier driving signal in response to a first sense amplifier control signal, and a second driving signal driver configured to drive via the transmission line the sense amplifier driving signal in response to a second sense amplifier control signal. The controller activates the first sense amplifier control signal in response to an active command, and toggles the second sense amplifier control signal while the first sense amplifier control signal is activated.

    摘要翻译： 半导体存储器件包括读出放大器，读出放大器驱动信号驱动器和控制器。 读出放大器被配置为响应于读出放大器驱动信号来检测和放大位线的信号和互补位线的信号。 读出放大器驱动信号驱动器包括：第一驱动信号驱动器，被配置为响应于第一读出放大器控制信号经由传输线驱动读出放大器驱动信号;以及第二驱动信号驱动器，被配置为通过传输线驱动读出放大器 响应于第二读出放大器控制信号的驱动信号。 控制器响应于有效命令激活第一读出放大器控制信号，并且在第一读出放大器控制信号被激活时切换第二读出放大器控制信号。

    Memory device and memory system comprising same
    6.
    发明授权
    Memory device and memory system comprising same 有权
    包含其的存储器件和存储器系统

    公开(公告)号：US08473694B2

    公开(公告)日：2013-06-25

    申请号：US12885728

    申请日：2010-09-20

    申请人： Dong-Hyuk Lee ,  Jung-Bae Lee ,  Ki-Won Park

    发明人： Dong-Hyuk Lee ,  Jung-Bae Lee ,  Ki-Won Park

    IPC分类号： G06F12/00

    CPC分类号： G11C29/08 ,  G11C11/401

    摘要： A memory device comprises a memory cell array comprising a plurality of memory blocks each comprising a plurality of memory cells and a control setting circuit. The control setting circuit divides the memory blocks into at least first and second groups based on whether each of the memory blocks comprises at least one substandard memory cell, and sets individually control parameters of the first and second groups. The substandard memory cells are identified based on test results of the memory cells with respect to at least one of the control parameters. Each memory block in the first group comprises at least one substandard memory cell, and each memory block in the second group comprises no substandard memory cell.

    摘要翻译： 存储器装置包括存储单元阵列，其包括多个存储块，每个存储块包括多个存储单元和控制设置电路。 控制设置电路基于每个存储器块是否包括至少一个不合标准的存储器单元，将存储器块分成至少第一组和第二组，并且分别设置第一组和第二组的控制参数。 基于存储器单元相对于至少一个控制参数的测试结果来识别不合格存储器单元。 第一组中的每个存储器块包括至少一个不合标准存储器单元，并且第二组中的每个存储器块都不包括不合格存储器单元。

    Semiconductor memory device having variable-mode refresh operation
    7.
    发明申请
    Semiconductor memory device having variable-mode refresh operation 审中-公开
    具有可变模式刷新操作的半导体存储器件

    公开(公告)号：US20100124138A1

    公开(公告)日：2010-05-20

    申请号：US12585317

    申请日：2009-09-11

    申请人： Dong-Hyuk Lee ,  Jung-Bae Lee

    发明人： Dong-Hyuk Lee ,  Jung-Bae Lee

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C8/10 ,  G11C7/1075 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C2211/4013

    摘要： A semiconductor memory device includes a bit line sense amplifier, a bit line pair that includes a bit line and a complementary bit line, the bit line and the complementary bit line of the bit line pair each being coupled to the bit line sense amplifier, a memory cell array having a plurality of memory banks, the memory banks including word lines and a plurality of memory cells, and a word line activation control unit that performs a control to access data corresponding to an externally same address in at least two memory cells by simultaneously activating a predetermined number of word lines from among the word lines sharing the bit line sense amplifier, and the word line activation control unit operates in response to a determination mode allowing signal that is set in accordance with a used memory density.

    摘要翻译： 半导体存储器件包括位线读出放大器，包括位线和互补位线的位线对，位线对的互补位线与位线读出放大器耦合， 具有多个存储体的存储单元阵列，所述存储体包括字线和多个存储器单元，以及字线激活控制单元，其执行控制以通过在至少两个存储器单元中访问对应于外部相同地址的数据进行控制 同时从共享位线读出放大器的字线中激活预定数量的字线，并且字线激活控制单元响应于根据所使用的存储器密度设置的确定模式允许信号来操作。

    Row address code selection based on locations of substandard memory cells
    8.
    发明授权
    Row address code selection based on locations of substandard memory cells 有权
    基于不合格存储单元位置的行地址码选择

    公开(公告)号：US08520461B2

    公开(公告)日：2013-08-27

    申请号：US12832208

    申请日：2010-07-08

    申请人： Dong-Hyuk Lee ,  Jung-Bae Lee ,  Ki-Won Park

    发明人： Dong-Hyuk Lee ,  Jung-Bae Lee ,  Ki-Won Park

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406 ,  G11C11/40618 ,  G11C11/40622 ,  G11C17/16 ,  G11C2211/4061

    摘要： A memory device identifies memory blocks that contain substandard memory cells. The memory device then determines row address codes to apply to the memory blocks during refresh operations. The row address codes determine which memory blocks of the memory block are refreshed together. The row address codes are designed to ensure that memory blocks having substandard memory cells, which must be refreshed more frequently than other cells, are refreshed together, while memory blocks without substandard memory cells are refreshed together.

    摘要翻译： 存储器设备识别包含不合标准存储器单元的存储器块。 然后，存储器件在刷新操作期间确定应用于存储器块的行地址代码。 行地址代码确定存储器块的哪些存储器块被一起刷新。 行地址码被设计为确保具有不同于其它单元的频率更新的不合格存储器单元的存储器块被一起刷新，而没有不合格存储器单元的存储器块被刷新在一起。

    ROW ADDRESS CODE SELECTION BASED ON LOCATIONS OF SUBSTANDARD MEMORY CELLS
    10.
    发明申请
    ROW ADDRESS CODE SELECTION BASED ON LOCATIONS OF SUBSTANDARD MEMORY CELLS 有权
    基于物理存储器单元的位置选择地址代码

    公开(公告)号：US20110069572A1

    公开(公告)日：2011-03-24

    申请号：US12832208

    申请日：2010-07-08

    申请人： Dong-Hyuk Lee ,  Jung-Bae Lee ,  Ki-Won Park

    发明人： Dong-Hyuk Lee ,  Jung-Bae Lee ,  Ki-Won Park

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406 ,  G11C11/40618 ,  G11C11/40622 ,  G11C17/16 ,  G11C2211/4061

    摘要： A memory device identifies memory blocks that contain substandard memory cells. The memory device then determines row address codes to apply to the memory blocks during refresh operations. The row address codes determine which memory blocks of the memory block are refreshed together. The row address codes are designed to ensure that memory blocks having substandard memory cells, which must be refreshed more frequently than other cells, are refreshed together, while memory blocks without substandard memory cells are refreshed together.

    摘要翻译： 存储器设备识别包含不合标准存储器单元的存储器块。 然后，存储器件在刷新操作期间确定应用于存储器块的行地址代码。 行地址代码确定存储器块的哪些存储器块被一起刷新。 行地址码被设计为确保具有不同于其它单元的频率更新的不合格存储器单元的存储器块被一起刷新，而没有不合格存储器单元的存储器块被刷新在一起。