公开(公告)号：US20220367696A1

公开(公告)日：2022-11-17

申请号：US17321992

申请日：2021-05-17

Applicant: CREE, INC.

Inventor： Thomas J. SMITH, JR. ,  Saptharishi SRIRAM ,  Charles W. RICHARDS, IV

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L21/76 ,  H01L21/765 ,  H01L29/66 ,  H02H3/06 ,  H02H3/12

Abstract: An apparatus includes a substrate; a group III-Nitride barrier layer; a source electrically coupled to the group III-Nitride barrier layer; a gate on the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; a p-region being arranged at or below the group III-Nitride barrier layer; and a recovery enhancement circuit configured to reduce an impact of an overload received by the gate. Additionally, at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, an area between the gate and the drain.

公开(公告)号：US20210104623A1

公开(公告)日：2021-04-08

申请号：US17123727

申请日：2020-12-16

Applicant: CREE, INC.

Inventor： Saptharishi SRIRAM ,  Thomas SMITH ,  Alexander SUVOROV ,  Christer HALLIN

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L29/40 ,  H01L29/10

Abstract: An apparatus includes a substrate. The apparatus further includes a group III-nitride buffer layer on the substrate; a group III-nitride barrier layer on the group III-nitride buffer layer, the group III-nitride barrier layer including a higher bandgap than a bandgap of the group III-nitride buffer layer. The apparatus further includes a source electrically coupled to the group III-nitride barrier layer; a gate electrically coupled to the group III-nitride barrier layer; a drain electrically coupled to the group III-nitride barrier layer; and a p-region being at least one of the following: in the substrate or on the substrate below said group III-nitride barrier layer.

公开(公告)号：US20220367697A1

公开(公告)日：2022-11-17

申请号：US17322199

申请日：2021-05-17

Applicant: CREE, INC.

Inventor： Christer HALLIN ,  Saptharishi SRIRAM ,  Jia GUO

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L21/76 ,  H01L21/765 ,  H01L29/66

Abstract: An apparatus configured to reduce lag includes a substrate; a group III-Nitride back barrier layer on the substrate; a group III-Nitride channel layer on the group III-Nitride back barrier layer; a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer include a higher bandgap than a bandgap of the group III-Nitride channel layer; a source electrically coupled to the group III-Nitride barrier layer; a gate on the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; and a p-region being arranged at or below the group III-Nitride barrier layer. Additionally, at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, an area between the gate and the drain.

公开(公告)号：US20220367695A1

公开(公告)日：2022-11-17

申请号：US17321963

申请日：2021-05-17

Applicant: CREE, INC.

Inventor： Thomas J. SMITH, Jr. ,  Saptharishi SRIRAM

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66 ,  H03K17/687

Abstract: An apparatus for reducing lag includes a substrate; a group III-Nitride barrier layer; a source electrically coupled to the group III-Nitride barrier layer; a gate on the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; a p-region being arranged at or below the group III-Nitride barrier layer; and a gate control circuit configured to control a gate voltage of the gate. Additionally, at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, and an area between the gate and the drain.

公开(公告)号：US20210167199A1

公开(公告)日：2021-06-03

申请号：US17172669

申请日：2021-02-10

Applicant: CREE, INC.

Inventor： Saptharishi SRIRAM ,  Jia GUO

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L29/40 ,  H01L29/10

Abstract: An apparatus to address gate lag effect and/or other negative performance includes a substrate; a group III-Nitride buffer layer on the substrate; a group III-Nitride barrier layer on the group III-Nitride buffer layer, the group III-Nitride barrier layer may include a higher bandgap than a bandgap of the group III-Nitride buffer layer; a source electrically coupled to the group III-Nitride barrier layer; a gate electrically coupled to the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; and a p-region being arranged at least in the substrate. In particular, the p-region extends toward a source side of the substrate; and the p-region extends toward a drain side of the substrate.