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公开(公告)号:US20180190815A1
公开(公告)日:2018-07-05
申请号:US15541661
申请日:2015-09-16
Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.
Inventor: Guangsheng ZHANG , Sen ZHANG , Peng BIAN , Xiaolong HU
IPC: H01L29/78 , H01L27/092 , H01L29/08 , H01L29/10 , H01L29/06 , H01L29/49 , H01L29/36 , H01L29/66 , H01L21/8238
CPC classification number: H01L29/7816 , H01L21/8238 , H01L21/823814 , H01L27/092 , H01L27/0922 , H01L29/0649 , H01L29/0865 , H01L29/0878 , H01L29/0882 , H01L29/1079 , H01L29/1095 , H01L29/36 , H01L29/42368 , H01L29/4916 , H01L29/66681 , H01L29/7817 , H01L29/7831 , H01L29/7835
Abstract: A high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor (10) comprises: a substrate (100); an N-type lateral double-diffused metal oxide semiconductor field effect transistor (200) formed on the substrate (100); and a P-type metal oxide semiconductor field effect transistor (300) formed at a drain of the N-type lateral double-diffused metal oxide semiconductor field effect transistor (200); wherein a gate of the P-type metal oxide semiconductor field effect transistor (300) serves as a gate of the high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor (10); a drain of the P-type metal oxide semiconductor field effect transistor (300) serves as a drain of the high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor (10); a source of the N-type lateral double-diffused metal oxide semiconductor field effect transistor (200) serves as a source of the high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor (10).
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公开(公告)号:US20170271505A1
公开(公告)日:2017-09-21
申请号:US15320589
申请日:2015-07-31
Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.
Inventor: Xiaolong HU , Guangsheng ZHANG , Peng BIAN , Sen ZHANG
CPC classification number: H01L29/7816 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/408 , H01L29/42368 , H01L29/4916 , H01L29/735 , H01L29/7831
Abstract: An N type lateral double-diffused metal oxide semiconductor field effect transistor (200) includes a substrate (202); a first N well (204) formed on the substrate; a second N well (206), a first P well (208), a third N well (210) and a fourth N well (212); a source lead-out region (214) formed on the first P well (208); a drain lead-out region (216) formed on the fourth N well (212); a first gate lead-out region formed on surfaces of the second N well (206) and the first P well (208); and a second gate lead-out region formed on surfaces of the first P well (208) and the third N well (210). The first gate lead-out region and the second gate lead-out region are respectively led out by means of metal wires, and then are connected to serve as a gate.
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