公开(公告)号：US20170062405A1

公开(公告)日：2017-03-02

申请号：US15308574

申请日：2015-05-04

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Guangsheng ZHANG ,  Sen ZHANG

IPC: H01L27/02 ,  H01L23/535 ,  H01L29/739

CPC classification number: H01L27/027 ,  H01L23/535 ,  H01L23/60 ,  H01L27/0266 ,  H01L29/7393 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a semiconductor device with an ESD protection structure. The semiconductor device includes a high-voltage power device 101, the ESD protection structure is a NMOS transistor 102, a drain of the NMOS transistor is shared by a source of the power device as a common-drain-source structure 107, substrate leading-out regions of the power device 101 and the NMOS transistor are coupled to the source 106 of the NMOS transistor as a ground leading-out. In the present disclosure, the drain of the NMOS transistor is shared by the source of the power device, so the increased area of the device with the ESD protection structure incorporated is small. In addition, the holding voltage at the source of the high-voltage power device is relatively low, which helps to protect the gate oxide and improve the source reliability.

Abstract translation: 本公开涉及具有ESD保护结构的半导体器件。 半导体器件包括高电压功率器件101，ESD保护结构是NMOS晶体管102，NMOS晶体管的漏极作为共漏极 - 源极结构107由功率器件的源共享， 功率器件101和NMOS晶体管的输出区域作为接地引出耦合到NMOS晶体管的源极106。 在本公开内容中，NMOS晶体管的漏极由功率器件的源共享，因此具有包含ESD保护结构的器件的增加的面积很小。 另外，高压功率器件源极的保持电压相对较低，有助于保护栅极氧化物，提高源极可靠性。

公开(公告)号：US20180190815A1

公开(公告)日：2018-07-05

申请号：US15541661

申请日：2015-09-16

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Guangsheng ZHANG ,  Sen ZHANG ,  Peng BIAN ,  Xiaolong HU

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L29/49 ,  H01L29/36 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/7816 ,  H01L21/8238 ,  H01L21/823814 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7831 ,  H01L29/7835

Abstract: A high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor (10) comprises: a substrate (100); an N-type lateral double-diffused metal oxide semiconductor field effect transistor (200) formed on the substrate (100); and a P-type metal oxide semiconductor field effect transistor (300) formed at a drain of the N-type lateral double-diffused metal oxide semiconductor field effect transistor (200); wherein a gate of the P-type metal oxide semiconductor field effect transistor (300) serves as a gate of the high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor (10); a drain of the P-type metal oxide semiconductor field effect transistor (300) serves as a drain of the high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor (10); a source of the N-type lateral double-diffused metal oxide semiconductor field effect transistor (200) serves as a source of the high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor (10).

公开(公告)号：US20160240659A1

公开(公告)日：2016-08-18

申请号：US15026193

申请日：2014-12-04

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Guangsheng ZHANG ,  Sen ZHANG

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7835 ,  H01L29/7838

Abstract: An LDMOS device, comprising a substrate (202), a gate electrode (211) on the substrate (202), a buried layer area in the substrate (202), and a diffusion layer on the buried layer area, wherein the buried layer area comprises a first buried layer (201) and a second buried layer (203), wherein the conduction types of impurities doped in the first buried layer (201) and the second buried layer (203) are opposite; the diffusion layer comprises a first diffusion area (205) and a second diffusion area (206), wherein the first diffusion area (205) is located on the first buried layer (201) and abuts against the first buried layer (201), and the second diffusion area (206) is located on the second buried layer (203) and abuts against the second buried layer (203); and the conduction types of impurities doped in the first buried layer (201) and the first diffusion area (205) are the same, and the conduction types of impurities doped in the second buried layer (203) and the second diffusion area (206) are the same. Additionally, also disclosed is a manufacturing method for the LDMOS device. A current path of the device in a conducting state is an area formed by the lower part of the second diffusion area (206) and the second buried layer (203) and is situated away from the surface of the device, so that the current capability of the device can be improved, the turn-on resistance can be reduced, and the reliability of the device can be improved.

Abstract translation: 一种LDMOS器件，包括衬底（202），在所述衬底（202）上的栅电极（211），所述衬底（202）中的掩埋层区域以及所述掩埋层区域上的扩散层，其中所述掩埋层区域 包括第一掩埋层（201）和第二掩埋层（203），其中掺杂在第一掩埋层（201）和第二掩埋层（203）中的杂质的传导类型相反; 所述扩散层包括第一扩散区域（205）和第二扩散区域（206），其中所述第一扩散区域（205）位于所述第一掩埋层（201）上并抵靠所述第一掩埋层（201），并且 所述第二扩散区域（206）位于所述第二掩埋层（203）上并与所述第二掩埋层（203）抵接; 并且掺杂在第一掩埋层（201）和第一扩散区域（205）中的杂质的导电类型相同，掺杂在第二掩埋层（203）和第二扩散区域（206）中的杂质的导电类型 是相同的。 此外，还公开了用于LDMOS器件的制造方法。 导通状态的器件的电流路径是由第二扩散区域（206）的下部和第二掩埋层（203）形成的并且远离器件表面的区域形成的区域，使得电流能力 的设备可以改善，可以降低导通电阻，并且可以提高器件的可靠性。

公开(公告)号：US20160233216A1

公开(公告)日：2016-08-11

申请号：US15023049

申请日：2014-12-03

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Guangsheng ZHANG ,  Sen ZHANG

IPC: H01L27/088 ,  H01L21/8236

Abstract: A semiconductor device includes a substrate (110); a buried layer (120) formed on the substrate (110), a diffusion layer (130) formed on the buried layer (120), wherein the diffusion layer (130) includes a first diffusion region (132) and a second diffusion region (134), and an impurity type of the second diffusion region (134) is opposite to an impurity type of the first diffusion region (132); the diffusion layer (134) further comprises a plurality of third diffusion regions (136) formed in the second diffusion region, wherein an impurity type of the third diffusion region (136) is opposite to the impurity type of the second diffusion region (134); and a gate (144) formed on the diffusion layer (130).

Abstract translation: 半导体器件包括衬底（110）; 形成在所述衬底（110）上的掩埋层（120），形成在所述掩埋层（120）上的扩散层（130），其中所述扩散层（130）包括第一扩散区域（132）和第二扩散区域 134），并且所述第二扩散区（134）的杂质类型与所述第一扩散区（132）的杂质类型相反; 扩散层（134）还包括形成在第二扩散区域中的多个第三扩散区域（136），其中第三扩散区域（136）的杂质类型与第二扩散区域（134）的杂质类型相反， ; 和形成在扩散层（130）上的栅极（144）。

公开(公告)号：US20170271505A1

公开(公告)日：2017-09-21

申请号：US15320589

申请日：2015-07-31

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Xiaolong HU ,  Guangsheng ZHANG ,  Peng BIAN ,  Sen ZHANG

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/49 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/735 ,  H01L29/7831

Abstract: An N type lateral double-diffused metal oxide semiconductor field effect transistor (200) includes a substrate (202); a first N well (204) formed on the substrate; a second N well (206), a first P well (208), a third N well (210) and a fourth N well (212); a source lead-out region (214) formed on the first P well (208); a drain lead-out region (216) formed on the fourth N well (212); a first gate lead-out region formed on surfaces of the second N well (206) and the first P well (208); and a second gate lead-out region formed on surfaces of the first P well (208) and the third N well (210). The first gate lead-out region and the second gate lead-out region are respectively led out by means of metal wires, and then are connected to serve as a gate.

公开(公告)号：US20170054018A1

公开(公告)日：2017-02-23

申请号：US15119868

申请日：2015-05-04

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Guangsheng ZHANG ,  Sen ZHANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A laterally diffused metal oxide semiconductor device includes: a substrate (10); a buried layer region (32) in the substrate; a well region (34) on the buried layer region (32); a gate region on the well region; a source region (41) and a drain region (43) which are located at two sides of the gate region; and a super junction structure. The source region (41) is located in the well region (34); the drain region (34) is located in the super junction structure; the gate region comprises a gate oxide layer and a gate electrode on the gate oxide layer; and the super junction structure comprises a plurality of N-columns and P-columns, wherein the N-columns and the P-columns are alternately arranged in a direction which is horizontal and is perpendicular to the direction of a connecting line between the source region and the drain region, each N-column comprises a top-layer N-region (23) and a bottom-layer N-region which are butted vertically, and each P-column comprises a top-layer P-region (24) and a bottom-layer P-region which are butted vertically.

Abstract translation: 横向扩散的金属氧化物半导体器件包括：衬底（10）; 衬底中的掩埋层区域（32）; 掩埋层区域（32）上的阱区（34）; 井区域上的栅极区域; 源区域（41）和漏极区域（43），位于栅极区域的两侧; 和超结结构。 源极区域（41）位于阱区域（34）中。 漏区（34）位于超结结构中; 栅极区域包括栅极氧化物层和栅极氧化物层上的栅电极; 并且超结结构包括多个N列和P列，其中N列和P列在水平方向上交替布置，并且垂直于源极区域之间的连接线的方向 和漏极区域，每个N列包括垂直对接的顶层N区（23）和底层N区，每个P列包括顶层P区（24）和 垂直对接的底层P区。