公开(公告)号：US20180012890A1

公开(公告)日：2018-01-11

申请号：US15547239

申请日：2015-09-23

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Wei LI ,  Long HAO ,  Yan JIN ,  Dejin WANG

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L29/45 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823462 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/088 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66492 ,  H01L29/66515 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7831

Abstract: A manufacturing method of a semiconductor device, comprising the following steps: providing a semiconductor substrate comprising a low-voltage device region and a high-voltage device region; forming first gate oxide layers in a non-gate region of the high-voltage device region and the low-voltage device region and a second gate oxide layer in a gate region of the high-voltage device region; the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer; forming a first polysilicon gate and a first sidewall structure on the surface of the first gate oxide layer of the low-voltage device region and a second polysilicon gate and a second sidewall structure on the surface of the second gate oxide layer; the width of the second gate oxide layer is greater than the width of the second polysilicon gate; performing source drain ions injection to form a source drain extraction region; after depositing a metal silicide area block (SAB), performing a photolithographic etching on the metal SAB and forming metal silicide. The above manufacturing method of a semiconductor device simplifies process steps and reduces process cost. The present invention also relates to a semiconductor device.

公开(公告)号：US20180019159A1

公开(公告)日：2018-01-18

申请号：US15548257

申请日：2016-01-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Wei LI ,  Long HAO ,  Yan JIN

IPC: H01L21/762 ,  H01L21/265 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/0217 ,  H01L21/26513 ,  H01L21/28105 ,  H01L21/28123 ,  H01L29/4983

Abstract: A manufacturing method for a semiconductor device, comprising: providing a semiconductor substrate (100), and forming a shallow trench isolation structure (104) in the semiconductor substrate (100); forming a gate structure comprising a gate oxidation layer (105a) and a gate material layer (105b) that are stacked from the bottom up on the semiconductor substrate (100); executing first ion implantation so as to form first doping ions in the gate material layer (105b), and executing second ion implantation (109) so as to form second doping ions at the part of the gate material layer (105b) that is located over a top corner of the shallow trench isolation structure(104), the second doping ions and the first doping ions being opposite in conduction type.