公开(公告)号：US20210126001A1

公开(公告)日：2021-04-29

申请号：US17257087

申请日：2019-10-12

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Song ZHANG ,  Zhibin LIANG ,  Yan JIN ,  Dejin WANG

IPC: H01L27/11521

Abstract: A flash device and a manufacturing method thereof. The method comprises: providing a substrate, and forming, on the substrate, a floating gate polycrystalline layer, a floating gate oxide layer, and a tunneling oxide layer; wherein the floating gate polycrystalline layer is formed on the substrate, the floating gate oxide layer is formed between the substrate and the floating gate polycrystalline layer, a substrate region at one side of the floating gate polycrystalline layer is a first substrate region, a substrate region at the other side of the floating gate polycrystalline layer is a second substrate region; forming, on the tunneling oxide layer, located in the first substrate region, a continuous non-conductive layer, the non-conductive layer extending to the tunneling oxide layer at a side wall of the floating gate polycrystalline layer; and forming, on the tunneling oxide layer, a polysilicon layer.

公开(公告)号：US20220069718A1

公开(公告)日：2022-03-03

申请号：US17420866

申请日：2020-06-19

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shen XU ,  Minggang CHEN ,  Wanqing YANG ,  Dejin WANG ,  Rui JIANG ,  Weifeng SUN ,  Longxing SHI

IPC: H02M3/335 ,  H02M1/38

Abstract: Disclosed are a system and method for controlling an active clamp flyback (ACF) converter. The system includes: a drive module configured to control turning-on or turning-off of a main switching transistor SL and a clamp switching transistor SH; a main switching transistor voltage sampling circuit configured to sample a voltage drop between an input terminal and an output terminal of the main switching transistor SL; a first comparator connected to the main switching transistor voltage sampling circuit and configured to determine whether a sampled first sampling voltage is a positive voltage or a negative voltage; and a dead time calculation module configured to adjust, according to an output of the first comparator and a main switching transistor control signal DUTYL of a current cycle, a clamp switching transistor control signal DUTYH of next cycle outputted by the drive module.

公开(公告)号：US20180012890A1

公开(公告)日：2018-01-11

申请号：US15547239

申请日：2015-09-23

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Wei LI ,  Long HAO ,  Yan JIN ,  Dejin WANG

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L29/45 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823462 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/088 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66492 ,  H01L29/66515 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7831

Abstract: A manufacturing method of a semiconductor device, comprising the following steps: providing a semiconductor substrate comprising a low-voltage device region and a high-voltage device region; forming first gate oxide layers in a non-gate region of the high-voltage device region and the low-voltage device region and a second gate oxide layer in a gate region of the high-voltage device region; the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer; forming a first polysilicon gate and a first sidewall structure on the surface of the first gate oxide layer of the low-voltage device region and a second polysilicon gate and a second sidewall structure on the surface of the second gate oxide layer; the width of the second gate oxide layer is greater than the width of the second polysilicon gate; performing source drain ions injection to form a source drain extraction region; after depositing a metal silicide area block (SAB), performing a photolithographic etching on the metal SAB and forming metal silicide. The above manufacturing method of a semiconductor device simplifies process steps and reduces process cost. The present invention also relates to a semiconductor device.

公开(公告)号：US20240290846A1

公开(公告)日：2024-08-29

申请号：US18572595

申请日：2022-04-28

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Qun LIU ,  Song ZHANG ,  Yaohui ZHOU ,  Dejin WANG ,  Wenming ZHU

IPC: H01L29/40 ,  H01L29/45

CPC classification number: H01L29/401 ,  H01L29/456

Abstract: A forming method for a floating contact hole, and a semiconductor device. The method comprises: obtaining a substrate, and forming a tunnel oxide layer and a plurality of gates on the substrate; forming a metal silicide barrier layer; forming a self-aligned metal silicide; forming an interlayer dielectric layer; performing photoetching on the interlayer dielectric layer to obtain a photoresist pattern, the photoresist pattern comprising a small adhesive strip in the middle of the floating contact hole; and etching the floating contact hole by using the photoresist pattern as an etching mask layer.

公开(公告)号：US20230019004A1

公开(公告)日：2023-01-19

申请号：US17762206

申请日：2020-09-25

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jiaxing WEI ,  Qichao WANG ,  Kui XIAO ,  Dejin WANG ,  Li LU ,  Ling YANG ,  Ran YE ,  Siyang LIU ,  Weifeng SUN ,  Longxing SHI

IPC: H01L29/78

Abstract: A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.

公开(公告)号：US20220069115A1

公开(公告)日：2022-03-03

申请号：US17417663

申请日：2019-12-19

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Siyang LIU ,  Chi ZHANG ,  Kui XIAO ,  Guipeng SUN ,  Dejin WANG ,  Jiaxing WEI ,  Li LU ,  Weifeng SUN ,  Shengli LU

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207

Abstract: A heterojunction semiconductor device with a low on-resistance includes a metal drain electrode, a substrate, and a buffer layer. A current blocking layer arranged in the buffer layer, a gate structure is arranged on the buffer layer, and the gate structure comprises a metal gate electrode, GaN pillars and AlGaN layers, wherein a metal source electrode is arranged above the metal gate electrode; and the current blocking layer comprises multiple levels of current blocking layers, the centers of symmetry of the layers are collinear, and annular inner openings of the current blocking layers at all levels gradually become smaller from top to bottom. The AlGaN layers and the GaN pillars are distributed in a honeycomb above the buffer layer.