公开(公告)号：US10797707B2

公开(公告)日：2020-10-06

申请号：US15741448

申请日：2016-05-10

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Xueyan Wang ,  Ying Yang ,  Jingjia Yu

IPC: H03L7/081 ,  H03L7/08 ,  H03L7/00

Abstract: A delay locked loop detection system (10), the system can be used for detecting the working state of a delay locked loop (400) and comprises: a signal generator (300), which is used for generating a reference clock and providing the reference clock to the delay locked loop (400); and a testing instrument (500), which is used for acquiring the clock signals output from the delay locked loop (400) and measuring whether the time delays thereof are consistent with expectations; the detection system (10) further comprises at least one of the following circuits: a pre-receiving circuit (100), which is used for receiving the reference clock from the signal generator (300) and amplifying and shaping the reference clock and then providing the reference clock to the delay locked loop (400); and a multiphase multiplexing circuit (200), which is used for receiving the clock signals output from the delay locked loop (400) and synthesizing and then providing a plurality of clock signals with different delay to the testing instrument (500). Also included is a delay locked loop detection method. The system and method mentioned above enable an accurate measurement for the delays of the delay locked loop.