公开(公告)号：US12165714B2

公开(公告)日：2024-12-10

申请号：US17916927

申请日：2021-04-28

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Bin Chen ,  Youhui Li ,  Ming Gu ,  Xinmiao Zhao ,  Hao Wang ,  Shuming Guo ,  Zongchuan Wang ,  Nan Zhang

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor memory, comprising a negative voltage providing unit, which is used for providing a first negative voltage to a word line during a read operation, and comprises: a clamping unit that comprises an input end, a control end and an output end, wherein the input end is coupled to a common ground end of the memory, and the control end is used for receiving a first signal; an energy storage capacitor, a first end of which is coupled to the output end, and a second end that is used for receiving a second signal; and a negative voltage providing end which is coupled to the first end, wherein the clamping unit is used for: pulling the voltage at the output end to the voltage at the input end when the first signal is “0”; and clamping the output end at a clamping voltage when the first signal is “1”.

公开(公告)号：US12130649B2

公开(公告)日：2024-10-29

申请号：US17799459

申请日：2020-12-09

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Youhui Li ,  Lijuan Zhu

IPC: G11C16/30 ,  G05F3/24

CPC classification number: G05F3/24 ,  G11C16/30

Abstract: A bias current generation circuit and a flash memory. The bias current generation circuit includes a voltage source, a switching circuit and a current generation circuit. The voltage source is configured to provide a voltage for generating a bias current. An input terminal of the switching circuit is connected to the voltage source, a control terminal of the switching circuit is configured to receive a control signal. The current generation circuit includes a first MOS transistor and a second MOS transistor, an input terminal and a control terminal of the first MOS transistor are connected to an output terminal of the switching circuit, an output terminal of the first MOS transistor is connected to an input terminal and a control terminal of the second MOS transistor, and an output terminal of the second MOS transistor is grounded.