公开(公告)号：US11188702B1

公开(公告)日：2021-11-30

申请号：US17139617

申请日：2020-12-31

Applicant: Cadence Design Systems, Inc.

Inventor： Bentian Jiang ,  Natarajan Viswanathan ,  William Robert Reece ,  Zhuo Li

IPC: G06F30/392 ,  G06F30/398 ,  G06F119/18

Abstract: Aspects of the present disclosure address systems and methods for local cluster refinement for integrated circuit (IC) designs using a dynamic weighting scheme. Initial cluster definitions are accessed. The initial cluster definitions define a plurality of clusters where each cluster includes a plurality of pins. Each cluster is evaluated with respect to one or more design rule constraints. Based on the evaluation, clusters are identified from the plurality of clusters. A set of refinement candidates are generated based on the one or more clusters. A scoring function that employs a dynamic weighting scheme is used to determine a refinement quality score for each refinement candidate in the set of candidates and one or more refinement candidates are selected from among the set of refinement candidates based on respective refinement quality scores. A refined clustering solution is generated based on the selected refinement candidates.

公开(公告)号：US11244099B1

公开(公告)日：2022-02-08

申请号：US17139675

申请日：2020-12-31

Applicant: Cadence Design Systems, Inc.

Inventor： Bentian Jiang ,  Natarajan Viswanathan ,  Zhuo Li ,  Yi-Xiao Ding

IPC: G06F30/396 ,  G06N20/00 ,  G06N5/04 ,  G06F30/3312 ,  G06F30/398 ,  G06F30/392

Abstract: Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of dock sinks during clock tree synthesis. An integrated circuit design comprising a clock net that includes a plurality of clock sinks is accessed. A set of clusters are generated by clustering the set of clock objects of the clock net. A machine-learning model is used to assess whether each cluster satisfies one or more design rule constraints. Based on determining each cluster in the set of dusters is assessed by the machine-learning model to satisfy the one or more design rule constraints, a timing analysis is performed to determine whether each cluster in the set of clusters satisfies the target timing constraints. A clustering solution for the clock net is generated based on the set of clusters in response to determining each cluster satisfies the one or more design rule constraints.

公开(公告)号：US11645441B1

公开(公告)日：2023-05-09

申请号：US17139657

申请日：2020-12-31

Applicant: Cadence Design Systems, Inc.

Inventor： Bentian Jiang ,  Natarajan Viswanathan ,  Zhuo Li ,  Yi-Xiao Ding

IPC: G06F30/3312 ,  G06N20/00 ,  G06F1/06

CPC classification number: G06F30/3312 ,  G06F1/06 ,  G06N20/00

Abstract: Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of clock sinks during clock tree synthesis. An integrated circuit (IC) design comprising a clock net that includes a plurality of clock sinks is accessed. An initial number of clusters to generate from the set of clock sinks is determined using a machine-learning model. A first set of clusters is generated from the set of clocks sinks and includes the initial number of clusters. A timing analysis is performed to determine whether each cluster in the first set of clusters satisfies design rule constraints. The initial number of clusters is adjusted based on the timing analysis and a clustering solution is generated based on the adjusted number of clusters.