公开(公告)号：US10963618B1

公开(公告)日：2021-03-30

申请号：US16735665

申请日：2020-01-06

Applicant: Cadence Design Systems, Inc.

Inventor： Amin Farshidi ,  William Robert Reece ,  Kwangsoo Han ,  Thomas Andrew Newton ,  Zhuo Li

IPC: G06F30/396 ,  G06F30/398 ,  G06F119/12 ,  G06F117/12 ,  G06F119/06 ,  G06F117/04

Abstract: Electronic design automation systems, methods, and media are presented for multi-dimension clock gate design in clock tree synthesis. In one embodiment, an input list of clock gate types is accessed, and the list is then used in generating a clock gate matrix. A circuit design with a clock tree is then accessed. The multi-dimensional design involves automatically selecting, for a first clock gate of the routing tree, a first clock gate type from the clock gate matrix based on a size and associated area for the first clock gate type to select a drive strength value for the first clock gate in the routing tree. The first clock gate is then resized to generate a resized first clock gate using the clock gate matrix to adjust a first delay value associated with the first clock gate while maintaining the drive strength value.

公开(公告)号：US10963617B1

公开(公告)日：2021-03-30

申请号：US16735658

申请日：2020-01-06

Applicant: Cadence Design Systems, Inc.

Inventor： Andrew Mark Chapman ,  William Robert Reece ,  Natarajan Viswanathan ,  Mehmet Can Yildiz ,  Gracieli Posser ,  Zhuo Li

IPC: G06F30/00 ,  G06F30/396 ,  G06F30/398 ,  G06F30/20 ,  G06F30/394

Abstract: Aspects of the present disclosure address systems and methods for fixing clock tree design constraint violations. An initial clock tree is generated. The generating of the initial clock tree comprises routing a clock net using an initial value for a parameter that controls a priority ratio between total route length and a maximum source-to-sink route length in each net of the clock tree. A violation to a clock tree design constraint is detected in the clock net in the clock tree, and based on detecting the violation, a rerouting candidate is generated by rerouting the clock net using an adjusted value for the parameter. A target clock tree is selected based on a comparison of timing characteristics of the rerouting candidate with the clock tree design constraint.

公开(公告)号：US10318693B1

公开(公告)日：2019-06-11

申请号：US15690043

申请日：2017-08-29

Applicant: Cadence Design Systems, Inc.

Inventor： Natarajan Viswanathan ,  Zhuo Li ,  Charles Jay Alpert ,  William Robert Reece ,  Thomas Andrew Newton

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods for designing an integrated circuit design clock tree structure with scaled-load balanced clusters. Consistent with some embodiments, the system may include a clock tree synthesis (CTS) tool configured to recursively group pins to form a set of clusters that are balanced according to a scaled load. During the recursive grouping, the CTS tool scales actual loads of clusters in accordance with a scaling factor that is based on the radius of the cluster. In this way, the scaling factor penalizes large cluster spans during recursive clustering, thereby producing a clock tree structure that meets design rule constraints.

公开(公告)号：US11188702B1

公开(公告)日：2021-11-30

申请号：US17139617

申请日：2020-12-31

Applicant: Cadence Design Systems, Inc.

Inventor： Bentian Jiang ,  Natarajan Viswanathan ,  William Robert Reece ,  Zhuo Li

IPC: G06F30/392 ,  G06F30/398 ,  G06F119/18

Abstract: Aspects of the present disclosure address systems and methods for local cluster refinement for integrated circuit (IC) designs using a dynamic weighting scheme. Initial cluster definitions are accessed. The initial cluster definitions define a plurality of clusters where each cluster includes a plurality of pins. Each cluster is evaluated with respect to one or more design rule constraints. Based on the evaluation, clusters are identified from the plurality of clusters. A set of refinement candidates are generated based on the one or more clusters. A scoring function that employs a dynamic weighting scheme is used to determine a refinement quality score for each refinement candidate in the set of candidates and one or more refinement candidates are selected from among the set of refinement candidates based on respective refinement quality scores. A refined clustering solution is generated based on the selected refinement candidates.

公开(公告)号：US10990721B1

公开(公告)日：2021-04-27

申请号：US16718018

申请日：2019-12-17

Applicant: Cadence Design Systems, Inc.

Inventor： William Robert Reece ,  Thomas Andrew Newton ,  Zhuo Li

IPC: G06F30/33 ,  G06F30/31 ,  G06F30/398

Abstract: Electronic design automation systems, methods, and media are presented for cell cloning during circuit design. In one embodiment, for a circuit design comprising a plurality of flip-flop elements having clock inputs provided by a routing tree, a delay is identified for each flip-flop element. The flip-flop elements are clustered by delay to generate at least two clusters of flip-flop elements. Elements within the clusters are then grouped by physical characteristics to generate delay groups of flip-flop elements. An updated routing tree is then generated for the circuit design using the first delay group and the second delay group.

公开(公告)号：US10402522B1

公开(公告)日：2019-09-03

申请号：US15692637

申请日：2017-08-31

Applicant: Cadence Design Systems, Inc.

Inventor： Natarajan Viswanathan ,  Charles Jay Alpert ,  Thomas Andrew Newton ,  William Robert Reece

IPC: G06F17/50

Abstract: Aspects of the present disclosure address improved systems and methods for region-aware clustering in integrated circuit (IC) designs. Consistent with some embodiments, the method may include identifying a clustering region for each clock driver included in an IC design based on locations of sinks and blockages, and timing constraints. The CTS tool finds representative locations for each clock driver within their respective clustering regions. Given the representative location for each clock driver, the CTS tool applies point-based clustering to the clock drivers of the IC design to obtain one or more clusters.

公开(公告)号：US11163929B1

公开(公告)日：2021-11-02

申请号：US16735672

申请日：2020-01-06

Applicant: Cadence Design Systems, Inc.

Inventor： William Robert Reece ,  Thomas Andrew Newton ,  Ruth Patricia Jackson ,  Zhuo Li

IPC: G06F30/337 ,  G06F117/04 ,  G06F30/398 ,  G06F119/12

Abstract: Various embodiments provide for clock network generation for a circuit design using an inverting integrated clock gate (ICG). According to some embodiments, a clock network with one or more inverting ICGs is generated, after a topology of the clock network is defined, by applying a non-inverting ICG-to-inverting ICG transform to one or more nodes of the clock network that comprise a non-inverting ICG. Additionally, according to some embodiments, a clock network is generated bottom-up (from the clock sinks to the root clock signal source) using one or more inverting ICGs.

公开(公告)号：US11132490B1

公开(公告)日：2021-09-28

申请号：US16735674

申请日：2020-01-06

Applicant: Cadence Design Systems, Inc.

Inventor： Ruth Patricia Jackson ,  William Robert Reece ,  Thomas Andrew Newton ,  Zhuo Li

IPC: G06F30/396 ,  G06F30/398 ,  G06F119/12 ,  G06F117/04

Abstract: Various embodiments provide for clock network generation for a circuit design using a negative-edge integrated clock gate (ICG). According to some embodiments, a clock network with one or more negative-edge ICGs is generated, after a topology of the clock network is defined, by applying a positive-edge ICG-to-negative-edge ICG transform to one or more nodes of the clock network that comprise a positive-edge ICG. Additionally, according to some embodiments, a clock network is generated bottom-up (from the clock sinks to the root clock signal source) using one or more negative-edge ICGs.

公开(公告)号：US10740532B1

公开(公告)日：2020-08-11

申请号：US16228432

申请日：2018-12-20

Applicant: Cadence Design Systems, Inc.

Inventor： William Robert Reece ,  Thomas Andrew Newton ,  Zhuo Li

IPC: G06F17/50 ,  G06F30/396 ,  G06F30/392 ,  G06F30/327 ,  G06F30/394 ,  G06F117/10 ,  G06F30/30 ,  G06F30/39

Abstract: Aspects of the present disclosure address improved systems and methods for generating a clock tree based on route-driven placement of fan-out clock drivers. Consistent with some embodiments, a method may include constructing a spanning tree comprising one or more paths that interconnect a set of clock sinks of a clock net of an integrated circuit device design. The method further includes calculating a center of the set of the clock sinks based on clock sink locations in the integrated circuit device design and identifying a point on the spanning tree nearest to the center of the set of clock sinks. The method further includes generating a clock tree by placing a clock driver at the point on the spanning tree that is nearest to the center of the set of clock sinks.

公开(公告)号：US10402533B1

公开(公告)日：2019-09-03

申请号：US15691631

申请日：2017-08-30

Applicant: Cadence Design Systems, Inc.

Inventor： William Robert Reece ,  Yi-Xiao Ding ,  Thomas Andrew Newton ,  Charles Jay Alpert ,  Zhuo Li

IPC: G06F17/50

Abstract: Systems, methods, media, and other such embodiments are described for placement of cells in a multi-level routing tree, where placement of a mid-level parent node between a grandparent node and a set of child nodes is not set. One embodiment involves generating a first routing subregion between a first set of child nodes associated with a first grandparent node and a first connecting route from the first routing subregion to the first grandparent node, which together are set as a first routing region comprising the first routing subregion and the first connecting route. Sampling points are selected along the first routing region, and for each sampling point a set of operating values associated with the sampling point is calculated. A position for the parent node is selected based on the operating values for the sampling points.