公开(公告)号：US11868695B1

公开(公告)日：2024-01-09

申请号：US17219730

申请日：2021-03-31

Applicant: Cadence Design Systems, Inc.

Inventor： Jhih-Rong Gao ,  Yi-Xiao Ding ,  Zhuo Li

IPC: G06F30/337 ,  G06F16/22

CPC classification number: G06F30/337 ,  G06F16/22

Abstract: Aspects of the present disclosure address systems and methods for driver resizing using a transition-based capacitance increase margin. An integrated circuit (IC) design stored in a database in memory is accessed. The IC design comprises a net comprising a set of driver cells. A capacitance increase margin for resizing an initial driver cell is determined based on a total capacitance of the net and transition time target associated with the initial driver cell. An alternative driver cell is selected from a library to resize the initial driver cell and is used to replace the initial driver cell in the net. The alternative driver is selected such that a pin capacitance of the alternative driver cell exceeds an initial pin capacitance corresponding to the initial driver cell by no more than the capacitance increase margin.

公开(公告)号：US10706201B1

公开(公告)日：2020-07-07

申请号：US16292012

申请日：2019-03-04

Applicant: Cadence Design Systems, Inc.

Inventor： Yi-Xiao Ding ,  Mehmet Can Yildiz

IPC: G06F30/30 ,  G06F30/394

Abstract: Various embodiments provide for circuit design routing using a track assignment based on a plurality of panels (also referred to herein as a multi-panel track assignment). According to some embodiments, a track assignment of a wire within a particular panel is performed based on a primary panel bound or limit and a secondary panel bound or limit. For instance, during a track assignment for a particular wire falling within a particular panel, an embodiment can first attempt to assign the particular wire to a track that falls within panels within the primary panel bound and, if deemed not possible (e.g., due to a DRC, violation or congestion issue), the embodiment can then assign the particular wire to a track that falls within panels within the secondary panel bound.

公开(公告)号：US10685164B1

公开(公告)日：2020-06-16

申请号：US16239310

申请日：2019-01-03

Applicant: Cadence Design Systems, Inc.

Inventor： Yi-Xiao Ding ,  Wing-Kai Chow ,  Gracieli Posser ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F17/50 ,  G06F30/394 ,  G06F111/04 ,  G06F111/20

Abstract: Various embodiments provide for circuit design routing based on parallel run length (PRL) rules. In particular, a plurality of PRL rules is accessed and used to generate a set of additional routing blockages around an existing routing blockage of the circuit design. The additional routing blockages can be positioned relative to the existing routing blockage. During routing, the set of additional routing blockages can be modeled into a capacity map, which is then used by global to generate routing guide(s) between at least two nodes of the circuit design. In doing so, the various embodiments can assist in routing a wire while avoiding violation of the plurality of PRL rules with respect to the existing blockage, can speed up performance of global routing, can make it easier for detailed routing to honor routing guides produced by global routing, and can speed up performance of detailed routing in resolving DRC violations.

公开(公告)号：US11514222B1

公开(公告)日：2022-11-29

申请号：US17207266

申请日：2021-03-19

Applicant: Cadence Design Systems, Inc.

Inventor： Sheng-En David Lin ,  Yi-Xiao Ding ,  Jhih-Rong Gao ,  Zhuo Li

IPC: G06F30/394 ,  G06F111/04 ,  G06F117/10

Abstract: An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises a routing topology for a net comprising interconnections between a set of pins. The IC design further comprises a set of candidate locations for inserting buffers. A set of cells from a cell library in memory is accessed. A candidate location from the set of candidate locations is assessed to determine whether at least one cell in the set of cells fits at the location. Based on determining that at least one cell in the set of cells fits at the candidate location, the location is marked as bufferable. A largest cell width that fits at the candidate location is determined based on the set of cells and a buffering solution is generated for the net using the largest cell width as a constraint on buffer insertion performed at the candidate location.

公开(公告)号：US11030378B1

公开(公告)日：2021-06-08

申请号：US16904534

申请日：2020-06-17

Applicant: Cadence Design Systems, Inc.

Inventor： Yi-Xiao Ding ,  Mehmet Can Yildiz ,  Zhuo Li

IPC: G06F30/3947 ,  G06F30/392

Abstract: Various embodiments described herein provide for track assignment of wires of a network of a circuit design by dynamic programming. In particular, various embodiments use a dynamic programming process to determine a set of breaking points for a routing wire of a global-routed and layer-assigned circuit design, and to determine track assignments for each of the sub-wires (sub-routes) formed by applying the set of selected breaking points to the routing wire. This results in a set of track-assigned sub-wires (or track-assigned sub-routes), which various embodiments can connect together to generate a connected set of track-assigned sub-wires that can be used in place of the routing wire.

公开(公告)号：US10936777B1

公开(公告)日：2021-03-02

申请号：US16777661

申请日：2020-01-30

Applicant: Cadence Design Systems, Inc.

Inventor： Jhih-Rong Gao ,  Yi-Xiao Ding ,  Zhuo Li

IPC: G06F30/00 ,  G06F30/337 ,  G06F30/392 ,  G06F30/31 ,  G06F30/396 ,  G06F30/3312

Abstract: Aspects of the present disclosure address improved systems and methods for rebuffering an integrated circuit (IC) design using a unified improvement scoring algorithm. A plurality of rebuffering candidates are generated based on an initial buffer tree in an integrated circuit (IC) design. A rebuffering candidate in the plurality of rebuffering candidates comprises a modified buffer tree based on the initial buffer tree. A buffering cost of each rebuffering candidate is determined. A reference buffer tree is selected from among the rebuffering candidates based on the buffering cost of each rebuffering candidate. An improvement score of each rebuffering candidate is determined based on the buffering cost of each rebuffering candidate relative to the reference buffer tree. A new buffer tree is selected from among the plurality of rebuffering candidates to replace the initial buffer tree based on the improvement score of each rebuffering candidate.

公开(公告)号：US10509878B1

公开(公告)日：2019-12-17

申请号：US15688730

申请日：2017-08-28

Applicant: Cadence Design Systems, Inc.

Inventor： Yi-Xiao Ding ,  Zhuo Li ,  Wen-Hao Liu

IPC: G06F17/50 ,  G06F1/10

Abstract: Systems, methods, media, and other such embodiments are described for routing track assignment in a circuit design. One embodiment involves accessing routing data for a circuit design, and a first wire of a plurality of wires in the routing data. A second wire is identified that is related to the first wire as a parent wire along a shared routing direction. A misalignment value is calculated for the first wire and the second wire, and a new routing placement is selected for the first wire based at least in part on the misalignment value. In some embodiments, all wires in various routings of a circuit design are checked for possible misalignment in order to improve slew performance via reduction of unnecessary vias.

公开(公告)号：US11675956B2

公开(公告)日：2023-06-13

申请号：US17219748

申请日：2021-03-31

Applicant: Cadence Design Systems, Inc.

Inventor： Jhih-Rong Gao ,  Yi-Xiao Ding ,  Zhuo Li

IPC: G06F30/30 ,  G06F30/398 ,  G06F30/392 ,  G06F111/04 ,  G06F117/10 ,  G06F119/12

CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F2111/04 ,  G06F2117/10 ,  G06F2119/12

Abstract: A system includes a machine configured to perform operations including accessing an integrated circuit design including a buffer tree that interconnects a plurality of inputs and buffers. The buffer tree includes a baseline timing characteristic. The operations include identifying a set of candidate solutions for improving the baseline timing characteristic using an initial timing model and selecting a subset of candidate solutions that have a timing characteristic lower than the baseline timing characteristic. Then the subset of candidate solutions are evaluated using a detailed timing model and based on determining that at least one candidate solution in the subset has a timing characteristic that is better than the baseline timing characteristic, selecting a candidate solution from the set of candidate solutions, and updating the buffer tree based on the candidate solution.

公开(公告)号：US11132489B1

公开(公告)日：2021-09-28

申请号：US16805155

申请日：2020-02-28

Applicant: Cadence Design Systems, Inc.

Inventor： Derong Liu ,  Yi-Xiao Ding ,  Zhuo Li ,  Mehmet Can Yildiz

IPC: G06F30/3947 ,  G06F30/398 ,  G06F30/392

Abstract: Various embodiments provide for layer assignment of a network of a circuit design based on a wirelength threshold, which can facilitate consideration of timing and electromigration and which may be part of electronic design automation (EDA) of a circuit design. More particularly, some embodiments determine (e.g., calculate) a wirelength threshold for a net (e.g., each net) of a circuit design based on one or more characteristics of the net, and select a layer for at least a portion of the net based on the wirelength threshold.

公开(公告)号：US10860764B1

公开(公告)日：2020-12-08

申请号：US16731912

申请日：2019-12-31

Applicant: Cadence Design Systems, Inc.

Inventor： Yi-Xiao Ding ,  Jhih-Rong Gao ,  Zhuo Li

IPC: G06F30/3312 ,  G06F30/337 ,  G06F30/392 ,  G06F30/3947 ,  G06F30/398 ,  G06F119/12 ,  G06F111/04 ,  G06F117/10

Abstract: Aspects of the present disclosure address improved systems and methods for layer assignment to improve timing in integrated circuit (IC) designs. An initial placement layout of a net of an IC design is accessed. A plurality of buffer insertion candidates is generated using multiple candidate buffer insertion points and multiple layer assignments from among multiple layers of the IC design. Timing characteristics of each buffer insertion candidate are determined, and timing improvements provided by each buffer insertion candidate are determined based on respective timing characteristics. A buffer insertion candidate is selected from the plurality of buffer insertion candidates based on the timing improvement provided by the buffer insertion candidate. A layout instance for the IC is generated based in part on the selected buffer insertion candidate.