公开(公告)号：US11190331B1

公开(公告)日：2021-11-30

申请号：US17124280

申请日：2020-12-16

Applicant: Cadence Design Systems, Inc.

Inventor： Loren B. Reiss ,  Scott David Huss ,  Fred Staples Stivers ,  James Dennis Vandersand, Jr.

IPC: H04L7/00

Abstract: A physical layer (PHY) device comprises a phase interpolator to generate a set of sampler clocks. A sampler of the PHY device samples a calibration data pattern based on the set of sampler clocks. A data alignment system of the PHY device performs a coarse calibration and a fine calibration on the sampler clock signals. During the coarse calibration, the data alignment system moves the sampler clock signals earlier or later in time relative to the sampled data based on a first bit of the sampled data. During the fine calibration, the data alignment system moves the sampler clock signals earlier or later in time relative to the sampled data based on the first bit, a second bit, and a third bit in the sampled data.

公开(公告)号：US11228416B1

公开(公告)日：2022-01-18

申请号：US16944036

申请日：2020-07-30

Applicant: Cadence Design Systems, Inc.

Inventor： Scott David Huss ,  Loren B. Reiss ,  Christopher George Moscone ,  James Dennis Vandersand, Jr.

IPC: H03K5/01 ,  H04L7/00 ,  H03K5/00

Abstract: Various embodiments provide for calibrating one or more clock signals for a serializer, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, for a serializer operating based on a plurality of clock signals, some embodiments provide for calibration of one or more of the plurality of clock signals by adjusting a duty cycle of one or more clock signals, a delay of one or more clock signals, or both.