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公开(公告)号：US11190331B1
公开(公告)日：2021-11-30
申请号：US17124280
申请日：2020-12-16
Applicant: Cadence Design Systems, Inc.
IPC: H04L7/00
Abstract: A physical layer (PHY) device comprises a phase interpolator to generate a set of sampler clocks. A sampler of the PHY device samples a calibration data pattern based on the set of sampler clocks. A data alignment system of the PHY device performs a coarse calibration and a fine calibration on the sampler clock signals. During the coarse calibration, the data alignment system moves the sampler clock signals earlier or later in time relative to the sampled data based on a first bit of the sampled data. During the fine calibration, the data alignment system moves the sampler clock signals earlier or later in time relative to the sampled data based on the first bit, a second bit, and a third bit in the sampled data.
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公开(公告)号：US11108425B1
公开(公告)日：2021-08-31
申请号：US17005092
申请日：2020-08-27
Applicant: Cadence Design Systems, Inc.
Inventor： Scott David Huss , Loren B. Reiss , Fred Staples Stivers , Matthew Robert Collin , James Lee House , Ramakrishna Kasukurthi
Abstract: A calibration control component within a transmit (TX) or receive (RX) device executes a calibration sequence to ensure reliable data transmission and reception within the device. The calibration sequence comprises a set of calibration functions that are sequentially executed. The calibration control component detects a pause function being enabled based on a pause function configuration register. Based on detecting the pause function being enabled, the calibration control component pauses execution of the calibration sequence.
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Patent Agency Ranking
公开(公告)号：US10992449B1
公开(公告)日：2021-04-27
申请号：US16940343
申请日：2020-07-27
Applicant: Cadence Design Systems, Inc.
Inventor： Loren B. Reiss , Fred Staples Stivers , Eric Harris Naviasky
Abstract: A set of encoders within a transmitter (TX) physical layer (PHY) encode incoming data using a predefined encoder scheme by translating multiple data segments into a set of balanced bit sequences. Each data segment comprises a first number of bits and each balanced bit sequence comprises a second number of bits. A data striping component distributes the set of balanced bit sequences to a set of serializers by routing bits from particular bit positions in each balanced bit sequence to a corresponding serializer. The set of serializers generates serialized data based on the set of balanced bit sequences.
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公开(公告)号：US11238204B1
公开(公告)日：2022-02-01
申请号：US17066284
申请日：2020-10-08
Applicant: Cadence Design Systems, Inc.
Inventor： Scott David Huss , Loren B. Reiss , Fred Staples Stivers , Steven Martin Broome
IPC: G06F30/30 , G01R31/317 , G01R31/3183 , G01R31/3187 , G06F30/333
Abstract: Various embodiments provide for testing a transmitter with interpolation, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, some embodiments provide for data transmission test of a transmitter by: generating and outputting a pre-determined data pattern through a serializer of the transmitter; sampling a serialized data output of the serializer over a plurality of different interpolation phase positions of a phase interpolator; and using a pattern checker to error check the sampled data over the plurality of different interpolation phase positions to determine whether the data transmission test passes.
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公开(公告)号：US11133793B1
公开(公告)日：2021-09-28
申请号：US17108941
申请日：2020-12-01
Applicant: Cadence Design Systems, Inc.
Inventor： Scott David Huss , Loren B. Reiss , Christopher George Moscone , Kelvin E. McCollough
Abstract: Various embodiments provide for phase interpolators with phase adjusters to provide step resolution, which can be used with a circuit such as a data serializer/deserializer circuit. In particular, for some embodiments, a phase interpolator is coupled to a phase adjuster, where the combination of the phase interpolator and the phase adjuster is configured to interpolate between phases in phase adjustment steps at a phase adjustment step resolution. For such embodiments, the phase adjustment step resolution of the steps is achieved by controlling the phase interpolator and the phase adjuster.
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公开(公告)号：US11228416B1
公开(公告)日：2022-01-18
申请号：US16944036
申请日：2020-07-30
Applicant: Cadence Design Systems, Inc.
Inventor： Scott David Huss , Loren B. Reiss , Christopher George Moscone , James Dennis Vandersand, Jr.
Abstract: Various embodiments provide for calibrating one or more clock signals for a serializer, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, for a serializer operating based on a plurality of clock signals, some embodiments provide for calibration of one or more of the plurality of clock signals by adjusting a duty cycle of one or more clock signals, a delay of one or more clock signals, or both.
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公开(公告)号：US11165553B1
公开(公告)日：2021-11-02
申请号：US17018529
申请日：2020-09-11
Applicant: Cadence Design Systems, Inc.
Inventor： Loren B. Reiss , Scott David Huss , Christopher George Moscone
Abstract: A phase interpolator of a physical layer (PHY) device comprise a phase interpolator to generate a set of asynchronous sampler clocks. A sampler of the PHY device samples a calibration data pattern using a first sampler clock from the set of asynchronous sampler clocks. A calibration control component of the PHY device detects a misalignment of a phase relationship among the set of asynchronous sampler clocks based on the sampled data. In response to detecting the misalignment, the calibration control component calibrates the first sampler clock using a second sampler clock and a third sampler clock.
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