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Patent Agency Ranking
公开(公告)号：US11133793B1
公开(公告)日：2021-09-28
申请号：US17108941
申请日：2020-12-01
Applicant: Cadence Design Systems, Inc.
Inventor： Scott David Huss , Loren B. Reiss , Christopher George Moscone , Kelvin E. McCollough
Abstract: Various embodiments provide for phase interpolators with phase adjusters to provide step resolution, which can be used with a circuit such as a data serializer/deserializer circuit. In particular, for some embodiments, a phase interpolator is coupled to a phase adjuster, where the combination of the phase interpolator and the phase adjuster is configured to interpolate between phases in phase adjustment steps at a phase adjustment step resolution. For such embodiments, the phase adjustment step resolution of the steps is achieved by controlling the phase interpolator and the phase adjuster.
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公开(公告)号：US10333533B1
公开(公告)日：2019-06-25
申请号：US16134656
申请日：2018-09-18
Applicant: Cadence Design Systems, Inc.
Inventor： Christopher George Moscone
IPC: H03L7/099
Abstract: Aspects of the present disclosure include systems, methods, devices, and circuits for correcting integral non-linearity using a hybrid phase interpolator. Consistent with some embodiments, a circuit comprises a first and second phase interpolator mixer connected to an injection-locked ring. The first phase interpolator mixer provides a first injection signal to the injection-locked ring based on a clock signal, and the second phase interpolator mixer provides a second injection signal to the injection-locked ring. The first and second injection signals have inverse step size profiles. The injection-locked ring generates a first and second output clock phase based on the first and second injection signals. In generating the first and second output clock phases, the injection-locked ring averages the step size profiles of the first and second injection signals.
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公开(公告)号：US11228416B1
公开(公告)日：2022-01-18
申请号：US16944036
申请日：2020-07-30
Applicant: Cadence Design Systems, Inc.
Inventor： Scott David Huss , Loren B. Reiss , Christopher George Moscone , James Dennis Vandersand, Jr.
Abstract: Various embodiments provide for calibrating one or more clock signals for a serializer, which can be used with a circuit for data communications, such as serializer/deserializer (SerDes) communications. In particular, for a serializer operating based on a plurality of clock signals, some embodiments provide for calibration of one or more of the plurality of clock signals by adjusting a duty cycle of one or more clock signals, a delay of one or more clock signals, or both.
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公开(公告)号：US11165553B1
公开(公告)日：2021-11-02
申请号：US17018529
申请日：2020-09-11
Applicant: Cadence Design Systems, Inc.
Inventor： Loren B. Reiss , Scott David Huss , Christopher George Moscone
Abstract: A phase interpolator of a physical layer (PHY) device comprise a phase interpolator to generate a set of asynchronous sampler clocks. A sampler of the PHY device samples a calibration data pattern using a first sampler clock from the set of asynchronous sampler clocks. A calibration control component of the PHY device detects a misalignment of a phase relationship among the set of asynchronous sampler clocks based on the sampled data. In response to detecting the misalignment, the calibration control component calibrates the first sampler clock using a second sampler clock and a third sampler clock.
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公开(公告)号：US10237052B1
公开(公告)日：2019-03-19
申请号：US15585348
申请日：2017-05-03
Applicant: Cadence Design Systems, Inc.
Inventor： Christopher George Moscone
Abstract: Systems and methods disclosed herein provide for effectively eliminating the rotational and static phase skews between the in-phase (I) and quadrature (Q) clocks generated by phase interpolators in decision feedback equalizer based receivers. Embodiments of the systems and methods provide for (i) a ring oscillator that eliminates the rotational phase skews and (ii) a plurality of clock mixers that eliminate the static phase skews.
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