公开(公告)号：US10782767B1

公开(公告)日：2020-09-22

申请号：US16176645

申请日：2018-10-31

Applicant: Cadence Design Systems, Inc.

Inventor： Karam Abd Elkader ,  Doron Bustan ,  Habeeb Farah ,  Yaron Schiller

IPC: G06F1/00 ,  G06F1/3237

Abstract: The present disclosure relates to a method for reducing power consumption. Embodiments include providing an electronic design of a device under test having a plurality of flip-flops associated therewith. Embodiments also include selecting a first set of flip-flops from the plurality of flip-flops and disabling a first clock associated with the first set of flip-flops without changing a value of the first set of flip-flops. Embodiments may further include selecting a second set of flip-flops from the plurality of flip-flops and disabling a second clock associated with the second set of flip-flops without changing a value of the second set of flip-flops. Embodiments may further include determining whether a first output from the first set of flip-flops and a second output from the second set of flip-flops have converged.

公开(公告)号：US11151295B1

公开(公告)日：2021-10-19

申请号：US17077187

申请日：2020-10-22

Applicant: Cadence Design Systems, Inc.

Inventor： Doron Bustan ,  Karam Abdelkader ,  Yaron Schiller

IPC: G06F30/3323 ,  G06F30/327

Abstract: A method for enhancing performance of SEC of two representations of an electronic design (with and without gated clock) includes selecting one or more pairs of correlated flip-flops (FFs), a first FF of each pair in the first representation toggled by the gated clock controlled by an enable combinational logic and a second FF of the pair, correlating to the first FF, in the second representation toggled by the constantly toggling clock. The method also includes defining a modified enable combinational logic for the gated clock, as a disjunction of the enable combinational logic of the gated clock and an enable combinational logic for each FF of a plurality of FFs that are toggled by the gated clock. The method also includes performing SEC on the two representations design, using the modified enable combinational logic for the gated clock instead of the enable combinational logic of the gated clock.

公开(公告)号：US11080448B1

公开(公告)日：2021-08-03

申请号：US16910815

申请日：2020-06-24

Applicant: Cadence Design Systems, Inc.

Inventor： Yaron Schiller ,  Guy Wolfovitz ,  Habeeb Farah

IPC: G06F30/30 ,  G06F30/3323 ,  G06F111/08 ,  G06F7/58

Abstract: A method for formal deep bug hunting in a device under test (DUT) may include obtaining a selection of a start state for the DUT; obtaining a selection of one or a plurality of variables that are declared as random variables; for each of said one or a plurality of random variables, generating a sequence of random values in a generation order using a random number generator (RNG); and performing formal verification exploration of the DUT starting at the start state and consecutively assigning each of said one or a plurality of random variables a value from the sequence of values in the generation order.

公开(公告)号：US10853546B1

公开(公告)日：2020-12-01

申请号：US16583937

申请日：2019-09-26

Applicant: Cadence Design Systems, Inc.

Inventor： Yaron Schiller ,  Almothana Sirhan ,  Karam Abdelkader ,  Habeeb Farah ,  Thiago Radicchi Roque

IPC: G06F30/3323 ,  G06F30/33

Abstract: A method for sequential equivalence checking (SEC) of two representations of an electronic design includes selecting by a processor a plurality of cutpoints in the two representations of the electronic design, rendering the two representations of the electronic design abstracted; executing by the processor an assume-guarantee (AG) proof on the two abstracted representations of the electronic design; identifying by the processor a failed assertion indicating non-equivalence of a signal pair relating to one of the cutpoints; and performing by the processor a simulation on the two representations of the electronic design by successively inputting input stimuli of a trace corresponding to the failed assertion in a sequential order in which the input stimuli appear in the trace at inputs of the two representations of the electronic design to identify whether there is one or a plurality of additional non-equivalent signal pairs relating to other cutpoints of said plurality of cutpoints.