公开(公告)号：US11545968B1

公开(公告)日：2023-01-03

申请号：US16877123

申请日：2020-05-18

Applicant: Cadence Design Systems, Inc.

Inventor： Moo Sung Chae ,  Thomas Evan Wilson

IPC: H03K5/1252 ,  G11C5/14 ,  H03H7/06 ,  H03F3/45

Abstract: Various embodiments provide for active suppression circuitry. The active suppression circuitry can be used with a circuit for a memory system, such as a dual data rate (DDR) memory system. For example, some embodiments provide an active suppression integrated circuit. The active suppression integrated circuit can be used by a memory system to efficiently suppress power supply noise caused by resonance of a power delivery network (PDN) of the memory system, thereby improving power integrity of the memory system input/output.

公开(公告)号：US10545895B1

公开(公告)日：2020-01-28

申请号：US15876473

申请日：2018-01-22

Applicant: Cadence Design Systems, Inc.

Inventor： Aaron Willey ,  Hari Anand Ravi ,  H. Md. Shuaeb Fazeel ,  Thomas Evan Wilson ,  Moo Sung Chae

IPC: G06F13/28

Abstract: Embodiments described herein relate to circuits and techniques for interfacing a microprocessor with memory devices, particularly memory devices such as DDR SDRAM in accordance with protocols such as DDR4 and DDR5. Some embodiments particularly relate to a receiver architecture for a DDR memory interface device that provides AC coupling to memory and includes auto-zeroing functionality. These and other embodiments incorporate equalization functionality such as decision feedback equalization and continuous time linear equalization.

公开(公告)号：US10128965B1

公开(公告)日：2018-11-13

申请号：US15694418

申请日：2017-09-01

Applicant: Cadence Design Systems, Inc.

Inventor： Thomas E. Wilson ,  Moo Sung Chae

IPC: H04B17/21 ,  H04B1/16

Abstract: A device including an input configured to receive an input signal in an operational mode and to receive a reference voltage in a calibration mode is provided. The device includes a capacitor to store a reference charge based on the reference voltage and an input inverter to capture a transition of the input signal. The input inverter is coupled in series with the capacitor so that the transition of the input signal occurs when a voltage of the input signal crosses the reference voltage. The device includes an output inverter coupled in series with the input inverter to provide an output signal having a parity of the input signal. A system including the above device, and a method for calibrating the above device, are also provided.