公开(公告)号：US10566046B1

公开(公告)日：2020-02-18

申请号：US16175577

申请日：2018-10-30

Applicant: Cadence Design Systems, Inc.

Inventor： Vinod Kumar ,  Thomas E. Wilson ,  Hari Anand Ravi

IPC: H03K3/00 ,  G11C11/4093 ,  H03K3/57 ,  H03K17/687

Abstract: Implementations described herein relate to circuits and techniques increasing transmitter output speed. In some implementations, a circuit is described using a pull-up data path comprising a first flying capacitor, a first buffer, a thin-oxide PMOS device, and a thick-oxide PMOS device, a pull-down data path comprising a second flying capacitor, a second buffer, a thin-oxide NMOS device, and a thick-oxide NMOS device, wherein the pull-up data path and the pull-down data path are operatively connected to a core data output signal line.

公开(公告)号：US09405314B1

公开(公告)日：2016-08-02

申请号：US14268825

申请日：2014-05-02

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Eric Naviasky ,  Thomas E. Wilson

IPC: G06F13/42 ,  G06F1/12 ,  G06F1/10

CPC classification number: G06F1/12 ,  G06F1/06 ,  G06F1/10

Abstract: A system and method are provided which incrementally samples and delays a signal passed through a transmission channel thereto. A receiver section is provided with a delay stage including a sample storage portion having a plurality of capacitors. A switch portion selectively switches the capacitors to respectively store incremental samples of the signal received through the channel. A clock source is provided to generate a plurality of periodic clock signals progressively shifted by a predefined clock phase increment. The clock source drives the switch portion to synchronously cycle the capacitors through at least sample and readout modes of operation, which are mutually offset in time by a preselected number of clock phase increments. The received signal is collectively reconstructed from the incremental samples of the capacitors, such that the reconstructed signal is delayed by the preselected number of clock phase increments.

Abstract translation: 提供了一种系统和方法，其逐渐对通过传输信道的信号采样和延迟。 接收器部分设置有包括具有多个电容器的样本存储部分的延迟级。 开关部分选择性地切换电容器以分别存储通过通道接收的信号的增量采样。 提供时钟源以产生逐渐偏移预定时钟相位增量的多个周期性时钟信号。 时钟源驱动开关部分，以通过至少采样和读出操作模式来同步地循环电容器，这些操作模式在时间上相互偏移预定数量的时钟相位增量。 接收的信号从电容器的增量采样中共同重建，使得重构信号被延迟预选数量的时钟相位增量。

公开(公告)号：US10128965B1

公开(公告)日：2018-11-13

申请号：US15694418

申请日：2017-09-01

Applicant: Cadence Design Systems, Inc.

Inventor： Thomas E. Wilson ,  Moo Sung Chae

IPC: H04B17/21 ,  H04B1/16

Abstract: A device including an input configured to receive an input signal in an operational mode and to receive a reference voltage in a calibration mode is provided. The device includes a capacitor to store a reference charge based on the reference voltage and an input inverter to capture a transition of the input signal. The input inverter is coupled in series with the capacitor so that the transition of the input signal occurs when a voltage of the input signal crosses the reference voltage. The device includes an output inverter coupled in series with the input inverter to provide an output signal having a parity of the input signal. A system including the above device, and a method for calibrating the above device, are also provided.

公开(公告)号：US11580048B1

公开(公告)日：2023-02-14

申请号：US16356939

申请日：2019-03-18

Applicant: Cadence Design Systems, Inc.

Inventor： Thomas E. Wilson ,  Scott Huss ,  Hari Anand Ravi ,  Sachin Ramesh Gugwad ,  Balbeer Singh Rathor

IPC: G06F9/30 ,  G06F13/42 ,  G06F1/12

Abstract: Various aspects of the subject technology relate to systems, methods, and machine-readable media for DDR reference voltage training. The method includes receiving a data stream, the data stream including pulses generated from a reference voltage in relation to a voltage input logic low and a voltage input logic high of an input stream. The method also includes receiving a clock signal, the clock signal including an in-phase signal and a quadrature-phase signal, the in-phase signal orthogonal to the quadrature-phase signal. The method also includes utilizing the in-phase signal and the quadrature-phase signal of the clock signal in relation to the data stream to obtain a stream of in-phase samples and a stream of quadrature-phase samples. The method also includes adjusting the reference voltage based on a relationship of the stream of in-phase samples to the stream of quadrature-phase samples.

公开(公告)号：US11483185B1

公开(公告)日：2022-10-25

申请号：US17246581

申请日：2021-04-30

Applicant: Cadence Design Systems, Inc.

Inventor： Sachin Ramesh Gugwad ,  Hari Anand Ravi ,  Aaron Willey ,  Thomas E. Wilson

IPC: H04L25/03

Abstract: Disclosed is an improved approach for a training approach to implement DFE for an electronic circuit. The inventive concept is particularity suitable to address, for example, circuits that implement high speed parallel data transmission protocols, such as GDDR6, that are used for graphics applications. The training scheme uses minimal hardware when compared to existing schemes by reusing calibration receiver in auto zeroing receiver as error receiver. Further it works for closed eyes by running the algorithm multiple times with gradual increase in complexity of training pattern, where DFE coefficients from previous iteration is used for the current iteration, thereby gradually opening the eye.