公开(公告)号：US10705984B1

公开(公告)日：2020-07-07

申请号：US16143123

申请日：2018-09-26

Applicant: Cadence Design Systems, Inc.

Inventor： H Md Shuaeb Fazeel ,  Nikhil Sawarkar ,  Aaron Willey ,  Thomas Evan Wilson

IPC: G06F13/16 ,  H03F3/45 ,  G06F30/30

Abstract: Embodiments relate to systems, methods, and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a plurality of receiver arrangements, each receiver arrangement having a sampling circuit and a multi-stage differential amplifier connected to the sampling circuit. Each receiver arrangement is configurable via switches between an amplifying mode and an autozero mode. Control circuitry may select output data from a sampling circuit of one or more receiver arrangements that are not in autozero mode. In various embodiments, settings for individual receiver arrangements may be set based on decision feedback equalization (DFE).

公开(公告)号：US10545895B1

公开(公告)日：2020-01-28

申请号：US15876473

申请日：2018-01-22

Applicant: Cadence Design Systems, Inc.

Inventor： Aaron Willey ,  Hari Anand Ravi ,  H. Md. Shuaeb Fazeel ,  Thomas Evan Wilson ,  Moo Sung Chae

IPC: G06F13/28

Abstract: Embodiments described herein relate to circuits and techniques for interfacing a microprocessor with memory devices, particularly memory devices such as DDR SDRAM in accordance with protocols such as DDR4 and DDR5. Some embodiments particularly relate to a receiver architecture for a DDR memory interface device that provides AC coupling to memory and includes auto-zeroing functionality. These and other embodiments incorporate equalization functionality such as decision feedback equalization and continuous time linear equalization.

公开(公告)号：US11483185B1

公开(公告)日：2022-10-25

申请号：US17246581

申请日：2021-04-30

Applicant: Cadence Design Systems, Inc.

Inventor： Sachin Ramesh Gugwad ,  Hari Anand Ravi ,  Aaron Willey ,  Thomas E. Wilson

IPC: H04L25/03

Abstract: Disclosed is an improved approach for a training approach to implement DFE for an electronic circuit. The inventive concept is particularity suitable to address, for example, circuits that implement high speed parallel data transmission protocols, such as GDDR6, that are used for graphics applications. The training scheme uses minimal hardware when compared to existing schemes by reusing calibration receiver in auto zeroing receiver as error receiver. Further it works for closed eyes by running the algorithm multiple times with gradual increase in complexity of training pattern, where DFE coefficients from previous iteration is used for the current iteration, thereby gradually opening the eye.

公开(公告)号：US10545889B1

公开(公告)日：2020-01-28

申请号：US16215603

申请日：2018-12-10

Applicant: Cadence Design Systems, Inc.

Inventor： H Md Shuaeb Fazeel ,  Nikhil Sawarkar ,  Aaron Willey ,  Thomas Evan Wilson

IPC: G11C11/4093 ,  G06F13/16 ,  G06F17/50 ,  H03F3/45

Abstract: Embodiments relate to systems, methods, and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a plurality of receiver arrangements, each receiver arrangement having a sampling circuit and a multi-stage differential amplifier connected to the sampling circuit. Each receiver arrangement is configurable via switches between an amplifying mode and an autozero mode. Control circuitry may select output data from receiver arrangements that are not in autozero mode using multiplexer circuitry. In various embodiments, settings for individual receiver arrangements may be set based on decision feedback equalization (DFE).