中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.015 seconds)

    Slew rate boosting for communication interfaces
    1.
    发明授权
    Slew rate boosting for communication interfaces 有权

    公开(公告)号：US11481148B1

    公开(公告)日：2022-10-25

    申请号：US17362352

    申请日：2021-06-29

    Applicant: Cadence Design Systems, Inc.

    Inventor： Vinod Kumar ,  Hajee Mohammed Shuaeb Fazeel ,  Thomas Evan Wilson

    IPC: G06F3/06 ,  H03K17/0412

    Abstract: This disclosure relates to slew rate boosting for communication interfaces. A circuit can include a driver circuit coupled to an output node and configured to provide a data signal to the output node based on an input signal. The data signal can a similar logical state as the input signal. The circuit can include a signal transition boosting circuit coupled to the output node and configured to provide a boosting signal to the output node based on the input signal and a charge pump delay adjustment signal. The charge pump delay adjustment signal can define an amount of time after which the boosting signal is provided to the output node. The boosting signal can be provided to the output node to signal boost the data signal for the amount of time defined by the charge pump delay adjustment signal to provide a boosted data signal at the output node.

    Voltage stress tolerant high speed memory driver having flying capacitor circuit
    2.
    发明授权
    Voltage stress tolerant high speed memory driver having flying capacitor circuit 有权

    公开(公告)号：US09754646B1

    公开(公告)日：2017-09-05

    申请号：US15342974

    申请日：2016-11-03

    Applicant: Cadence Design Systems, Inc.

    Inventor： Vinod Kumar ,  Tara Vishin ,  Sachin Ramesh Gugwad ,  Thomas Evan Wilson

    IPC: G11C7/12 ,  G11C7/10 ,  G11C7/22

    CPC classification number: G11C7/1012 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093

    Abstract: Embodiments relate to circuits, electronic design automation (EDA) circuit layouts, systems, methods, and computer readable media to enable logic devices operating on a core supply voltage to drive memory devices operating on a different supply voltage using low power and high data rates while avoiding voltage over-stress of thin-oxide transistors. In an embodiment, channels of a thin-oxide PMOS transistor, a thick-oxide PMOS transistor, a thick-oxide NMOS transistor, and a thin-oxide NMOS transistor are coupled in order from a memory device voltage supply rail to a low voltage supply rail. Gates of the thin-oxide PMOS transistor and the thick-oxide NMOS transistor are coupled with an output of a flying capacitor circuit that level-shifts an input signal by a difference between the memory device supply and core supply voltages, while gates of the thick-oxide PMOS transistor and the thin-oxide NMOS transistor receive the input signal via a buffer.

    Active suppression circuitry
    5.
    发明授权
    Active suppression circuitry 有权

    公开(公告)号：US11545968B1

    公开(公告)日：2023-01-03

    申请号：US16877123

    申请日：2020-05-18

    Applicant: Cadence Design Systems, Inc.

    Inventor： Moo Sung Chae ,  Thomas Evan Wilson

    IPC: H03K5/1252 ,  G11C5/14 ,  H03H7/06 ,  H03F3/45

    Abstract: Various embodiments provide for active suppression circuitry. The active suppression circuitry can be used with a circuit for a memory system, such as a dual data rate (DDR) memory system. For example, some embodiments provide an active suppression integrated circuit. The active suppression integrated circuit can be used by a memory system to efficiently suppress power supply noise caused by resonance of a power delivery network (PDN) of the memory system, thereby improving power integrity of the memory system input/output.

    High-speed low VT drift receiver
    6.
    发明授权
    High-speed low VT drift receiver 有权

    公开(公告)号：US10705984B1

    公开(公告)日：2020-07-07

    申请号：US16143123

    申请日：2018-09-26

    Applicant: Cadence Design Systems, Inc.

    Inventor： H Md Shuaeb Fazeel ,  Nikhil Sawarkar ,  Aaron Willey ,  Thomas Evan Wilson

    IPC: G06F13/16 ,  H03F3/45 ,  G06F30/30

    Abstract: Embodiments relate to systems, methods, and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a plurality of receiver arrangements, each receiver arrangement having a sampling circuit and a multi-stage differential amplifier connected to the sampling circuit. Each receiver arrangement is configurable via switches between an amplifying mode and an autozero mode. Control circuitry may select output data from a sampling circuit of one or more receiver arrangements that are not in autozero mode. In various embodiments, settings for individual receiver arrangements may be set based on decision feedback equalization (DFE).

    Dual path phase-locked loop circuit
    9.
    发明授权
    Dual path phase-locked loop circuit 有权

    公开(公告)号：US10389368B1

    公开(公告)日：2019-08-20

    申请号：US15943491

    申请日：2018-04-02

    Applicant: Cadence Design Systems, Inc.

    Inventor： Fuyue Wang ,  Ling Chen ,  Thomas Evan Wilson ,  Jianyun Zhang ,  Eric Harris Naviasky

    IPC: H03L7/06 ,  H03L7/089 ,  H03L7/093 ,  H03L7/099

    Abstract: Aspects of the present disclosure include a dual path phase locked loop (PLL) circuit with a switched capacitor filter topology along with systems, method, devices, and other circuits related thereto. The dual path PLL circuit includes an integral path and a proportional path. Both the integral path and proportional path include a charge pump and a loop filter. The outputs of a phase frequency detector (PFD) are sent to both charge pumps. The output of the integral path charge pump is connected to a capacitor, and the voltage on capacitor is used as the integral path control voltage for a voltage-controlled oscillator (VCO). A switched capacitor network is connected to the output of the proportional path charge pump and used to generate the proportional path control voltage for the VCO. Together, the two control voltages dictate the VCO's output frequency.

    Methods and devices for a memory interface receiver
    10.
    发明授权
    Methods and devices for a memory interface receiver 有权

    公开(公告)号：US10193555B1

    公开(公告)日：2019-01-29

    申请号：US15197324

    申请日：2016-06-29

    Applicant: Cadence Design Systems, Inc.

    Inventor： Eric Harris Naviasky ,  Thomas Evan Wilson

    IPC: G06F17/50 ,  H03K19/0948 ,  G11C14/00 ,  H03F1/30 ,  G11C11/412 ,  H03K17/687

    Abstract: Embodiments relate to systems, methods and computer readable media to enable design and creation of receiver circuitry One embodiment is a receiver apparatus comprising a first resistor connected to a first receiver input, a first N-type metal oxide semiconductor (NMOS) field effect transistor (FET), a second NMOS FET, a trans-impedance amplifier wherein an input terminal of the trans-impedance amplifier is connected to a drain terminal of the second NMOS FET, and a complementary metal oxide semiconductor (CMOS) logic gate. Additional embodiments including other circuitry, associated methods, and media comprising instructions associated with generation of circuit design files are also described.

Patent Agency Ranking