公开(公告)号：US11979262B1

公开(公告)日：2024-05-07

申请号：US17569978

申请日：2022-01-06

Applicant: Cadence Design Systems, Inc.

Inventor： Hari Anand Ravi ,  Sachin Ramesh Gugwad

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/03267

Abstract: Various embodiments provide for identifying and training a floating tap for decision feedback equalization. For some embodiments, the identification and training of the floating tap described herein can be part of a circuit for receiver block of a system, such as a memory system.

公开(公告)号：US10566046B1

公开(公告)日：2020-02-18

申请号：US16175577

申请日：2018-10-30

Applicant: Cadence Design Systems, Inc.

Inventor： Vinod Kumar ,  Thomas E. Wilson ,  Hari Anand Ravi

IPC: H03K3/00 ,  G11C11/4093 ,  H03K3/57 ,  H03K17/687

Abstract: Implementations described herein relate to circuits and techniques increasing transmitter output speed. In some implementations, a circuit is described using a pull-up data path comprising a first flying capacitor, a first buffer, a thin-oxide PMOS device, and a thick-oxide PMOS device, a pull-down data path comprising a second flying capacitor, a second buffer, a thin-oxide NMOS device, and a thick-oxide NMOS device, wherein the pull-up data path and the pull-down data path are operatively connected to a core data output signal line.

公开(公告)号：US12184286B1

公开(公告)日：2024-12-31

申请号：US17831685

申请日：2022-06-03

Applicant: Cadence Design Systems, Inc.

Inventor： Prakash Kumar Lenka ,  Hari Anand Ravi ,  Jitendra Kumar Yadav

IPC: H03K5/00 ,  G01R29/02 ,  H03K3/017 ,  H03K5/24

Abstract: The present disclosure describes a circuit that may include a first amplifier portion configured to receive a first input signal corresponding to a first clock signal and a second input signal corresponding to a second clock signal. The circuit may include a first amplifier of the first amplifier portion. The first amplifier may be configured to receive a first amplifier input signal and a second amplifier input signal. The circuit may include a second amplifier portion configured to receive a first output signal from the first amplifier portion. In a first mode, the first amplifier input signal may be based upon the second input signal and the second amplifier input signal may be based upon the first input signal. In a second mode, the first amplifier input signal may be based upon the first input signal and the second amplifier input signal may be based upon the second input signal.

公开(公告)号：US11580048B1

公开(公告)日：2023-02-14

申请号：US16356939

申请日：2019-03-18

Applicant: Cadence Design Systems, Inc.

Inventor： Thomas E. Wilson ,  Scott Huss ,  Hari Anand Ravi ,  Sachin Ramesh Gugwad ,  Balbeer Singh Rathor

IPC: G06F9/30 ,  G06F13/42 ,  G06F1/12

Abstract: Various aspects of the subject technology relate to systems, methods, and machine-readable media for DDR reference voltage training. The method includes receiving a data stream, the data stream including pulses generated from a reference voltage in relation to a voltage input logic low and a voltage input logic high of an input stream. The method also includes receiving a clock signal, the clock signal including an in-phase signal and a quadrature-phase signal, the in-phase signal orthogonal to the quadrature-phase signal. The method also includes utilizing the in-phase signal and the quadrature-phase signal of the clock signal in relation to the data stream to obtain a stream of in-phase samples and a stream of quadrature-phase samples. The method also includes adjusting the reference voltage based on a relationship of the stream of in-phase samples to the stream of quadrature-phase samples.

公开(公告)号：US11483185B1

公开(公告)日：2022-10-25

申请号：US17246581

申请日：2021-04-30

Applicant: Cadence Design Systems, Inc.

Inventor： Sachin Ramesh Gugwad ,  Hari Anand Ravi ,  Aaron Willey ,  Thomas E. Wilson

IPC: H04L25/03

Abstract: Disclosed is an improved approach for a training approach to implement DFE for an electronic circuit. The inventive concept is particularity suitable to address, for example, circuits that implement high speed parallel data transmission protocols, such as GDDR6, that are used for graphics applications. The training scheme uses minimal hardware when compared to existing schemes by reusing calibration receiver in auto zeroing receiver as error receiver. Further it works for closed eyes by running the algorithm multiple times with gradual increase in complexity of training pattern, where DFE coefficients from previous iteration is used for the current iteration, thereby gradually opening the eye.

公开(公告)号：US12205673B1

公开(公告)日：2025-01-21

申请号：US17945902

申请日：2022-09-15

Applicant: Cadence Design Systems, Inc.

Inventor： Hari Anand Ravi ,  Sachin Ramesh Gugwad ,  Jitendra Kumar Yadav ,  Thomas Evan Wilson ,  Vinod Kumar

IPC: G11C8/18 ,  G06F1/12 ,  G06F13/20 ,  G11C7/22

Abstract: Various embodiments described herein provide for a read data strobe (RDQS) path having variation compensation (e.g., voltage and temperature compensation), delay lines, or both, where the RDQS path can be included by a physical (PHY) interface for a memory device, such as a Double Data Rate (DDR) Dynamic Random-Access Memory (DRAM) memory device.

公开(公告)号：US12183427B1

公开(公告)日：2024-12-31

申请号：US17967040

申请日：2022-10-17

Applicant: Cadence Design Systems, Inc.

Inventor： Sachin Ramesh Gugwad ,  Hari Anand Ravi

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/14 ,  G11C7/22

Abstract: The present disclosure relates to a system and method for duty cycle correction is provided. The method may include receiving a signal at a duty cycle adjuster and performing serializer clock duty cycle correction at the duty cycle adjuster. The method may further include performing true clock duty cycle correction at a transmitter duty cycle adjuster and performing complementary duty cycle distortion correction at the transmitter duty cycle adjuster.

公开(公告)号：US10545895B1

公开(公告)日：2020-01-28

申请号：US15876473

申请日：2018-01-22

Applicant: Cadence Design Systems, Inc.

Inventor： Aaron Willey ,  Hari Anand Ravi ,  H. Md. Shuaeb Fazeel ,  Thomas Evan Wilson ,  Moo Sung Chae

IPC: G06F13/28

Abstract: Embodiments described herein relate to circuits and techniques for interfacing a microprocessor with memory devices, particularly memory devices such as DDR SDRAM in accordance with protocols such as DDR4 and DDR5. Some embodiments particularly relate to a receiver architecture for a DDR memory interface device that provides AC coupling to memory and includes auto-zeroing functionality. These and other embodiments incorporate equalization functionality such as decision feedback equalization and continuous time linear equalization.

公开(公告)号：US12289111B1

公开(公告)日：2025-04-29

申请号：US17972814

申请日：2022-10-25

Applicant: Cadence Design Systems, Inc.

Inventor： Hari Anand Ravi

IPC: H04L7/00 ,  H03L7/08 ,  H04L7/033

Abstract: The present disclosure relates to a system and method for clock phase recovery. Embodiments may include sampling data using an in-phase clock and a quadrate phase clock. Embodiments may further include analyzing sampled data from the in-phase clock and the quadrate phase clock. Embodiments may also include determining a convergence point based upon, at least in part, the analyzed sampled data, wherein the convergence point corresponds to a point where a number of early sampled outcomes is approximately equal to a number of late sampled outcomes. Embodiments may also include dynamically updating an accumulator threshold based upon the convergence point.

公开(公告)号：US11323296B1

公开(公告)日：2022-05-03

申请号：US16943535

申请日：2020-07-30

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Sachin Ramesh Gugwad ,  Hari Anand Ravi ,  Thomas E Wilson ,  Vinod Kumar

IPC: H04L25/03 ,  H04L27/01

Abstract: The embodiments described herein provide for a method and system for training an optimal decision feedback equalization (DFE) coefficient for use in GDDR and DDR applications. The method includes determining a first expected bit pattern using a reference voltage. The method further includes determining a transition voltage value of the first expected bit pattern. The method further includes receiving a second expected bit pattern having a same first bit as the first expected bit pattern. The method further includes determining a transition voltage value of the second expected bit pattern using the reference voltage. The method further includes calculating an optimal reference voltage value by averaging the transition voltage values of the first expected bit pattern and the second-expected bit pattern and storing the optimal reference voltage value in a register corresponding to a logic value of the same first bit.