公开(公告)号：US12205673B1

公开(公告)日：2025-01-21

申请号：US17945902

申请日：2022-09-15

Applicant: Cadence Design Systems, Inc.

Inventor： Hari Anand Ravi ,  Sachin Ramesh Gugwad ,  Jitendra Kumar Yadav ,  Thomas Evan Wilson ,  Vinod Kumar

IPC: G11C8/18 ,  G06F1/12 ,  G06F13/20 ,  G11C7/22

Abstract: Various embodiments described herein provide for a read data strobe (RDQS) path having variation compensation (e.g., voltage and temperature compensation), delay lines, or both, where the RDQS path can be included by a physical (PHY) interface for a memory device, such as a Double Data Rate (DDR) Dynamic Random-Access Memory (DRAM) memory device.

公开(公告)号：US12184286B1

公开(公告)日：2024-12-31

申请号：US17831685

申请日：2022-06-03

Applicant: Cadence Design Systems, Inc.

Inventor： Prakash Kumar Lenka ,  Hari Anand Ravi ,  Jitendra Kumar Yadav

IPC: H03K5/00 ,  G01R29/02 ,  H03K3/017 ,  H03K5/24

Abstract: The present disclosure describes a circuit that may include a first amplifier portion configured to receive a first input signal corresponding to a first clock signal and a second input signal corresponding to a second clock signal. The circuit may include a first amplifier of the first amplifier portion. The first amplifier may be configured to receive a first amplifier input signal and a second amplifier input signal. The circuit may include a second amplifier portion configured to receive a first output signal from the first amplifier portion. In a first mode, the first amplifier input signal may be based upon the second input signal and the second amplifier input signal may be based upon the first input signal. In a second mode, the first amplifier input signal may be based upon the first input signal and the second amplifier input signal may be based upon the second input signal.

公开(公告)号：US11876521B1

公开(公告)日：2024-01-16

申请号：US17729088

申请日：2022-04-26

Applicant: Cadence Design Systems, Inc.

Inventor： Hajee Mohammed Shuaeb Fazeel ,  Jitendra Kumar Yadav ,  Thomas Evan Wilson

IPC: H03K5/134 ,  H03L7/081 ,  H03K5/00

CPC classification number: H03K5/134 ,  H03L7/0818 ,  H03K2005/00195

Abstract: The present disclosure relates to dynamically updating a delay line code. A method for updating the delay line code may include receiving a strobe input at a coarse delay line. The method may further include receiving a coarse delay cell code at the coarse delay line. The method may also include generating a first clock path based upon a first chain of interleaved logic gates included within the coarse delay line. The method may additionally include generating a second clock path based upon a second chain of interleaved logic gates included within the coarse delay line. The method may further include receiving the first clock path, and the second clock path, and a fine delay cell code at a fine delay cell. The method may also include generating a strobe delayed output based upon the first clock path, and the second clock path, and the fine delay code.