公开(公告)号：US11531803B1

公开(公告)日：2022-12-20

申请号：US17232616

申请日：2021-04-16

Applicant: Cadence Design Systems, Inc.

Inventor： Umesh Gupta ,  Naresh Kumar ,  Marut Agarwal ,  Rakesh Agarwal

IPC: G06F30/398 ,  G06F119/12

Abstract: A static timing analysis system for finding and reporting timing violations in a digital circuit design prior to circuit fabrication, and associated methods, use exhaustive path-based analysis (EPBA) that is informed by infinite-depth path-based analysis (IPBA) to provide analysis results that are driven full-depth, in contrast to conventional EPBA systems and methods, which can terminate after reaching a maximum depth of analysis as a way of avoiding prolonged or infinite runtimes. The IPBA-driven full-depth EPBA functions for hold-mode as well as setup-mode analysis and achieves reduced pessimism as compared to systems or methods employing IPBA alone, and more complete analysis of designs as compared to systems or methods employing EPBA alone. Improved IPBA signal merging using multidimensional zones for thresholding of signal clustering mitigates the occasional optimism of IPBA.

公开(公告)号：US10915685B1

公开(公告)日：2021-02-09

申请号：US16222638

申请日：2018-12-17

Applicant: Cadence Design Systems, Inc.

Inventor： Umesh Gupta ,  Naresh Kumar ,  Rakesh Agarwal ,  Sukriti Khanna ,  Jayant Sharma ,  Ritika Govila

IPC: G06F17/50 ,  G06F30/3312 ,  G06F30/327 ,  G06F30/394 ,  G06F111/04 ,  G06F111/20 ,  G06F119/12

Abstract: The present embodiments relate to static timing analysis (STA) of circuits. The STA can include determining graph based analysis (GBA) delays of timing paths within the circuit. Path based analysis (PBA) delays of a subset of timing paths can be determined to generate circuit stage credit values for circuit stages in the circuit. The circuit stage credit values can be used to adjust GBA delays of the timing paths. Prediction functions can be utilized to predict or estimate PBA delays of timing paths thereby avoiding the determination of actual PBA delays of the timing paths.