公开(公告)号：US10776547B1

公开(公告)日：2020-09-15

申请号：US16600927

申请日：2019-10-14

Applicant: Cadence Design Systems, Inc.

Inventor： Umesh Gupta ,  Naresh Kumar ,  Prashant Sethia ,  Ritika Govila ,  Jayant Sharma

IPC: G06F30/3312 ,  G06F16/901 ,  G06F119/12

Abstract: A static timing analysis system for finding timing violations in a digital circuit design prior to circuit fabrication, and associated methods, use infinite-depth path-based analysis (IPBA) to achieve reduced pessimism as opposed to systems or methods employing only graph-based analysis (GBA), but with greatly reduced compute time requirements, or greater logic path coverage, versus systems or methods employing conventional or exhaustive path-based analysis. IPBA achieves the improved coverage or compute time results by slotting nodes of a circuit design graph into stages, propagating phases stage-by-stage for all paths in parallel, and merging phases wherever possible during the analysis.

公开(公告)号：US10915685B1

公开(公告)日：2021-02-09

申请号：US16222638

申请日：2018-12-17

Applicant: Cadence Design Systems, Inc.

Inventor： Umesh Gupta ,  Naresh Kumar ,  Rakesh Agarwal ,  Sukriti Khanna ,  Jayant Sharma ,  Ritika Govila

IPC: G06F17/50 ,  G06F30/3312 ,  G06F30/327 ,  G06F30/394 ,  G06F111/04 ,  G06F111/20 ,  G06F119/12

Abstract: The present embodiments relate to static timing analysis (STA) of circuits. The STA can include determining graph based analysis (GBA) delays of timing paths within the circuit. Path based analysis (PBA) delays of a subset of timing paths can be determined to generate circuit stage credit values for circuit stages in the circuit. The circuit stage credit values can be used to adjust GBA delays of the timing paths. Prediction functions can be utilized to predict or estimate PBA delays of timing paths thereby avoiding the determination of actual PBA delays of the timing paths.

公开(公告)号：US11531803B1

公开(公告)日：2022-12-20

申请号：US17232616

申请日：2021-04-16

Applicant: Cadence Design Systems, Inc.

Inventor： Umesh Gupta ,  Naresh Kumar ,  Marut Agarwal ,  Rakesh Agarwal

IPC: G06F30/398 ,  G06F119/12

Abstract: A static timing analysis system for finding and reporting timing violations in a digital circuit design prior to circuit fabrication, and associated methods, use exhaustive path-based analysis (EPBA) that is informed by infinite-depth path-based analysis (IPBA) to provide analysis results that are driven full-depth, in contrast to conventional EPBA systems and methods, which can terminate after reaching a maximum depth of analysis as a way of avoiding prolonged or infinite runtimes. The IPBA-driven full-depth EPBA functions for hold-mode as well as setup-mode analysis and achieves reduced pessimism as compared to systems or methods employing IPBA alone, and more complete analysis of designs as compared to systems or methods employing EPBA alone. Improved IPBA signal merging using multidimensional zones for thresholding of signal clustering mitigates the occasional optimism of IPBA.

公开(公告)号：US09589096B1

公开(公告)日：2017-03-07

申请号：US14716059

申请日：2015-05-19

Applicant: Cadence Design Systems, Inc.

Inventor： Umesh Gupta ,  Vishnu Kumar ,  Manish Bansal ,  Naresh Kumar ,  Manuj Verma ,  Prashant Sethia

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5036 ,  G06F2217/84

Abstract: Methods and systems provide setup and generation of SPICE results for a set of timing path(s) and integration of SPICE simulation with static timing analysis (STA) path-based results generation. In an embodiment, a method may select a candidate set of timing paths, perform path based analysis (PBA) on the selected paths, generate SPICE results for the selected paths, and render the PBA and SPICE results in an integrated user interface to facilitate sign off based on annotated constraints and correlation between STA results and SPICE results. Methods and systems of the present disclosure find application in, among other things, timing signoff in an electronic design and verification process.

Abstract translation: 方法和系统提供SPICE结果的设置和生成，用于一组定时路径以及SPICE仿真与静态时序分析（STA）基于路径的结果生成的集成。 在一个实施例中，方法可以选择候选的定时路径集合，在所选择的路径上执行基于路径的分析（PBA），为所选择的路径生成SPICE结果，并将PBA和SPICE结果呈现在集成的用户界面中以便于签名 基于注释约束和STA结果与SPICE结果之间的相关性。 本公开的方法和系统尤其涉及在电子设计和验证过程中的定时签发。

公开(公告)号：US10114920B1

公开(公告)日：2018-10-30

申请号：US15197142

申请日：2016-06-29

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Umesh Gupta ,  Shashank Tripathi ,  Naresh Kumar ,  Arvind Nembili Veeravalli ,  Prashant Sethia ,  Ritika Govila

IPC: G06F17/50

Abstract: A netlist of a multiple voltage circuit design having a plurality of power domains is established, then inter-power domain (IPD) paths traversing the circuit design are identified, according to whether they traverse multi-supply elements, or are clock paths capturing such a path. The netlist is then pruned to disable or remove cells or stages not traversed by an IPD path. A timing analyzer conducts a multi-domain timing analysis of the IPD timing paths in the pruned IPD netlist. Thereby, the circuit design is thoroughly tested according to the applicable ranges of voltage conditions without excessive runtime.

公开(公告)号：US08863052B1

公开(公告)日：2014-10-14

申请号：US13940576

申请日：2013-07-12

Applicant: Cadence Design Systems, Inc.

Inventor： Amit Dhuria ,  Naresh Kumar ,  Umesh Gupta ,  Pradeep Yadav ,  Prashant Sethia

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A system and method are provided for generating a structurally-aware timing model for operation of a predetermined circuit design. The timing model is generated to have a plurality of timing arcs representing timing characteristics of the circuit design. Additionally, terminal pairs of the circuit design are evaluated to determine characteristic structural weights for selected paths through the circuit design. The structurally-aware timing model may then be incorporated into a top-level hierarchical circuit design for timing analyses and pessimism removal to arrive at realistic timing characteristics. The structural weights are particularly helpful in an AOCV-type pessimism removal post-process.

Abstract translation: 提供了一种用于产生用于预定电路设计的操作的结构感知定时模型的系统和方法。 产生定时模型以具有表示电路设计的定时特性的多个定时弧。 另外，评估电路设计的端子对以确定通过电路设计的所选路径的特征结构权重。 结构感知定时模型然后可以被并入到顶级分级电路设计中，用于定时分析和悲观消除以达到实际的定时特性。 结构重量在AOCV型悲观消除后期处理中特别有用。